FEDEVEL
Platform forum

095126 , 03-01-2024, 02:32 AM

Hi @Robert Feranec I am a pcb layout engineer and I have a question, can I give a polygon in between the two PCIe4.0 differential line? Because I cannot find any answer over the internet. I followed most of the layout guidelines of the PCIe4.0. And I have lots of space on the board to give ground polygons.

QDrives , 03-01-2024, 02:38 PM

Do you mean to place copper (polygon) between two differential pairs?
Yes, if you add sufficient stiching vias. Do note, that the impedance my change a bit due to the additional copper.
And do not forget about copper balancing.

095126 , 03-01-2024, 04:28 PM

The thing is For PCIe4.0 5W clearance is required and the board is of 24 layers so I have plenty of space in other layers majorly on differential routing.

095126 , 03-01-2024, 04:30 PM

Yes and those differential pairs have 8 GHz of signal speed as per the PCIe4.0

Robert Feranec , 03-01-2024, 04:43 PM

I agree with @QDrives

QDrives , 03-01-2024, 09:02 PM

I forgot to mention that Robert made a video with Eric Bogatin, but I do not know exactly which one. Perhaps this one:

QDrives , 03-01-2024, 09:02 PM

https://www.youtube.com/watch?v=U60y4JC0Wxs

095126 , 03-02-2024, 03:11 AM

Thanks I hope this works, and also it will provide copper balancing in my pcb