FEDEVEL
Platform forum

M.Mazighe , 09-15-2025, 09:40 PM

Dear Mr.@Robert Feranec,
Dear Mr. @Phil,

I’m developing a new PCB with DDR3L memory as part of my Advanced Digital Hardware Design course.
I noticed that in some devkits, the order of the LDM and UDM input signals is different, even though the data (DQ) assignment order stays similar.

Could you please confirm that this is correct, as long as the physical and logical assignments stay consistent?

Also, would it be possible to share the Altium project files related to this design? It would help me understand the implementation and support my development.

Thanks a lot for your help!

Robert Feranec , 09-15-2025, 10:46 PM

DM0 is related to data bank D0-7, DM1 is related to data bank D8-D15, so DM connection depends on what CPU data signals you connect to Lower (L) data pins on the memory chip and what SPU signals you connect to the Upper (U) data pins on the memory chip.

Robert Feranec , 09-15-2025, 10:46 PM

This may help: https://youtu.be/aySAg50S1E8

Robert Feranec , 09-15-2025, 10:47 PM

Full altium files for that project are not available, but you can have a look at our open source projects on https://www.imx6rex.com/

M.Mazighe , 09-16-2025, 12:41 AM

Thank you so much for your support and for sharing these resources, this is fantastic and really helpful.
I appreciate your time and guidance!