<div class="entry-content">
    <div class="jetpack-video-wrapper"><span class="embed-youtube" style="text-align:center; display: block;"><iframe
                class="youtube-player"
                src="https://www.youtube.com/embed/9B66SqaYCZs?version=3&rel=1&showsearch=0&showinfo=1&iv_load_policy=1&fs=1&hl=en&autohide=2&wmode=transparent"
                allowfullscreen="true"
                style="border: 0px; display: block; margin: 0px; width: 740px; height: 416.418px;"
                sandbox="allow-scripts allow-same-origin allow-popups allow-presentation"
                data-ratio="0.5627272727272727" data-width="1100" data-height="619"></iframe></span>
    </div>
    <div class="blog-content">
        How the model of PCB used in high speed board simulations is created. Explained by Eric Bogatin. Thank you Eric.
    </div>
    <div class="blog-content-chapters">
        <div>
            Chapters:
        </div>
        <ul class="chapters-list">
            <li class="chapters-list-item">
                <span class="chapters-time">00:00</span><span class="chapters-text">What is this video about</span>
            </li>
            <li class="chapters-list-item">
                <span class="chapters-time">00:29</span><span class="chapters-text">What are s-Parameters, Why we need them</span>
            </li>
            <li class="chapters-list-item">
                <span class="chapters-time">05:51</span><span class="chapters-text">How S-Parameters models are created</span>
            </li>
            <li class="chapters-list-item">
                <span class="chapters-time">08:02</span><span class="chapters-text">Including components in simulations with S-Parameters</span>
            </li>
            <li class="chapters-list-item">
                <span class="chapters-time">14:44</span><span class="chapters-text">What is in S-Parameters file?</span>
            </li>
            <li class="chapters-list-item">
                <span class="chapters-time">17:10</span><span class="chapters-text">Opening and explaining S-Parameters file</span>
            </li>
            <li class="chapters-list-item">
                <span class="chapters-time">23:04</span><span class="chapters-text">S-Parameters ports explained – what they are</span>
            </li>
            <li class="chapters-list-item">
                <span class="chapters-time">26:09</span><span class="chapters-text">Floating ports</span>
            </li>
            <li class="chapters-list-item">
                <span class="chapters-time">30:23</span><span class="chapters-text">S-Parameters numbers explained</span>
            </li>
            <li class="chapters-list-item">
                <span class="chapters-time">30:59</span><span class="chapters-text">What ports to use when using S-Parameters model</span>
            </li>
        </ul>
    </div>
    <div class="blog-content-links">
        <div>
            Links:
        </div>
        <ul class="links-list">
            <li class="links-list-item"><a href="https://www.bethesignal.com/bogatin/3monthsubscription.php">Signal Integrity Academy (use FEDSI - 3 months free)</a></li>
            <li class="links-list-item"><a href="https://fedevel.com/courses">FEDEVEL courses</a></li>
        </ul>
    </div>   
</div>

Must Know This to Understand High Speed PCB Layout Simulation | S-Parameters Explained, Eric Bogatin

<div class="entry-content">
    <div class="jetpack-video-wrapper"><span class="embed-youtube" style="text-align:center; display: block;"><iframe
                class="youtube-player"
                src="https://www.youtube.com/embed/kdCJxdR7L_I?version=3&rel=1&showsearch=0&showinfo=1&iv_load_policy=1&fs=1&hl=en&autohide=2&wmode=transparent"
                allowfullscreen="true"
                style="border: 0px; display: block; margin: 0px; width: 740px; height: 416.418px;"
                sandbox="allow-scripts allow-same-origin allow-popups allow-presentation"
                data-ratio="0.5627272727272727" data-width="1100" data-height="619"></iframe></span>
    </div>
    <div class="blog-content">
        Maybe you don’t need extra power layers in your PCB and using tracks for power distribution may be just ok. An interesting discussion with Eric Bogatin.
    </div>
    <div class="blog-content-chapters">
        <div>
            Chapters:
        </div>
        <ul class="chapters-list">
            <li class="chapters-list-item">
                <span class="chapters-time">00:00</span><span class="chapters-text">What is this video about</span>
            </li>
            <li class="chapters-list-item">
                <span class="chapters-time">00:35</span><span class="chapters-text">Maximum current through a PCB track</span>
            </li>
            <li class="chapters-list-item">
                <span class="chapters-time">03:40</span><span class="chapters-text">Stackups: SGSS, SGSG, GSSG (S – Signal, G – GND)</span>
            </li>
            <li class="chapters-list-item">
                <span class="chapters-time">10:31</span><span class="chapters-text">Stackups SGGS vs SGPS (P – Power)</span>
            </li>
            <li class="chapters-list-item">
                <span class="chapters-time">37:10</span><span class="chapters-text">Real examples – Measured noise</span>
            </li>
            <li class="chapters-list-item">
                <span class="chapters-time">54:55</span><span class="chapters-text">Real examples – Emissions</span>
            </li>
        </ul>
    </div>
    <div class="blog-content-links">
        <div>
            Links:
        </div>
        <ul class="links-list">
            <li class="links-list-item"><a href="https://www.bethesignal.com/bogatin/3monthsubscription.php">Signal Integrity Academy (use FEDSI - 3 months free)</a></li>
            <li class="links-list-item"><a href="https://fedevel.com/courses">FEDEVEL courses</a></li>
        </ul>
    </div>   
</div>

Do You Really Need Power Planes? Are you sure? | Eric Bogatin

<div class="entry-content">
    <div class="jetpack-video-wrapper"><span class="embed-youtube" style="text-align:center; display: block;"><iframe
                class="youtube-player"
                src="https://www.youtube.com/embed/yQIBS5xwvVQ?version=3&rel=1&showsearch=0&showinfo=1&iv_load_policy=1&fs=1&hl=en&autohide=2&wmode=transparent"
                allowfullscreen="true"
                style="border: 0px; display: block; margin: 0px; width: 740px; height: 416.418px;"
                sandbox="allow-scripts allow-same-origin allow-popups allow-presentation"
                data-ratio="0.5627272727272727" data-width="1100" data-height="619"></iframe></span>
    </div>
    <div class="blog-content">
        Watch this animation to understand better how a signal is lost when travelling through a VIA.
    </div>
    <div class="blog-content-chapters">
        <div>
            Chapters:
        </div>
        <ul class="chapters-list">
            <li class="chapters-list-item">
                <span class="chapters-time">00:00</span><span class="chapters-text">What is this video about</span>
            </li>
            <li class="chapters-list-item">
                <span class="chapters-time">01:14</span><span class="chapters-text">Example 1: Single ended, no stitching VIA</span>
            </li>
            <li class="chapters-list-item">
                <span class="chapters-time">06:08</span><span class="chapters-text">Example 2: Single ended, 1 stitching VIA</span>
            </li>
            <li class="chapters-list-item">
                <span class="chapters-time">10:17</span><span class="chapters-text">Example 3: Single ended, 2 and 6 stitching VIAs</span>
            </li>
            <li class="chapters-list-item">
                <span class="chapters-time">12:43</span><span class="chapters-text">VIA Analyzer – How far we can place stitching VIAs and how many we need</span>
            </li>
            <li class="chapters-list-item">
                <span class="chapters-time">16:50</span><span class="chapters-text">Post layout analyzes</span>
            </li>
            <li class="chapters-list-item">
                <span class="chapters-time">21:14</span><span class="chapters-text">Changing VIA impedance</span>
            </li>
            <li class="chapters-list-item">
                <span class="chapters-time">32:45</span><span class="chapters-text">Example 4: Differential pair, no stitching VIA</span>
            </li>
            <li class="chapters-list-item">
                <span class="chapters-time">36:10</span><span class="chapters-text">Example 5: Differential pair, 2 stitching VIAs</span>
            </li>
            <li class="chapters-list-item">
                <span class="chapters-time">48:18</span><span class="chapters-text">1x VIA + 1x stitching VIA return current</span>
            </li>
            <li class="chapters-list-item">
                <span class="chapters-time">55:20</span><span class="chapters-text">About the software we were using + Prices</span>
            </li>
        </ul>
    </div>
    <div class="blog-content-links">
        <div>
            Links:
        </div>
        <ul class="links-list">
            <li class="links-list-item"><a href="https://youtu.be/vrt3lL5gEb0">Unexpected Currents On The Other Side Of GND Plane</a></li>
            <li class="links-list-item"><a href="https://www.linkedin.com/in/yuriy-shlepnev-7b39136/">Yuriy's Linkedin</a></li>
            <li class="links-list-item"><a href="https://www.simberian.com/">Yuriy's website</a></li>
        </ul>
    </div>   
</div>


NOT in the Copper! 3D Animation of a Signal Through a VIA | Yuriy Shlepnev

<div class="entry-content"> <p>I setup a new forum for Electronic Enthusiastics &amp; Professionals. It already has some interesting posts. I like this one about simulating CPU -&gt; FLASH &amp; SDRAM connection: <a href="http://www.fedevel.com/designhelp/forum/test/pcb-layout/82-sdr-sdram-layout-recommendations" target="_blank">SDR SDRAM layout recommendations</a>. </p> <p>The post is all about making decision on, how to place &amp; route CPU + FLASH + SDRAM on one shared bus. <strong>Have a look at the simulations and notice the signal quality difference for different routing topology.</strong></p> <div align="center"><i><b>The worst case</b><br> Placing series termination resistor close to the CPU (U1, input, blue color), setting up MEMORY as Output (U2, green), routing all parts in one line (I did not actually placed the chips in one line, as there will be some tracks inside the package, so I made a small stub)</i></div> <div align="center">â€‹<p></p> <div class="size_fullsize"><img class="bbcode-attachment thumbnail" src="http://www.fedevel.com/designhelp/filedata/fetch?id=118&amp;d=1441387698&amp;type=full" alt="Click image for larger version Name:  Simulation - R near CPU - Inline.png Views: 1 Size: 102.9 KB ID:  60" border="0"></div> <div class="size_fullsize"><img class="bbcode-attachment thumbnail" src="http://www.fedevel.com/designhelp/filedata/fetch?id=119&amp;d=1441387902&amp;type=full" alt="Click image for larger version Name:  Simulation - R near CPU - Inline.png Views: 1 Size: 135.8 KB ID:  61" border="0"></div> <div style="height:40px;"></div> <p><i><b>The optimum case</b><br> Placing series termination resistor close to the SDRAM, setting up MEMORY as Output (green color), routing all the branches same length</i></p> <div class="size_fullsize"><img class="bbcode-attachment thumbnail" src="http://www.fedevel.com/designhelp/filedata/fetch?id=120&amp;d=1441388101&amp;type=full" alt="Click image for larger version Name: Simulation - R near MEM - Tbranch.png Views:  1 Size: 161.8 KB ID:  62" border="0"></div> <div class="size_fullsize"><img class="bbcode-attachment thumbnail" src="http://www.fedevel.com/designhelp/filedata/fetch?id=121&amp;d=1441388282&amp;type=full" alt="Click image for larger version Name:  Simulation - R near MEM - Tbranch.png Views:  1 Size: 132.4 KB ID:  63" border="0"></div> </div> <p>Read more at the forum: <a href="http://www.fedevel.com/designhelp/forum/test/pcb-layout/82-sdr-sdram-layout-recommendations" target="_blank">http://www.fedevel.com/designhelp/forum/test/pcb-layout/82-sdr-sdram-layout-recommendations</a></p> </div>

Forum for Everyone Interested in Schematic & PCB Design

<div class="entry-content"> <p>During PCB layout, you have to decide on clearance between traces. Here are 3 key factors you may need to consider:</p> <h2>1) Manufacturing capabilities</h2> <p>Check with your PCB manufacturer, what is the minimum gap they can actually manufacture. Many PCB manufacturers have it on their website, as an example check this <a href="http://www.sqpinternational.com/capabilities.php" target="_blank">SQP International</a>. <i>Note: Normally I do not use clearance smaller than 0.1mm (4mil).</i></p> <h2>2) Signal requirements</h2> <p>For critical signals, you may want to use a bigger clearance as is the minimum manufacturing gap. One of the main factors to consider is crosstalk (as you know, signals routed close to each other can influence each other). If you are not sure how big the gap should be, you can use a Crosstalk calculator e.g. download <a href="http://www.saturnpcb.com/pcb_toolkit.htm" target="_blank">Saturn PCB Toolkint</a> -&gt; Crosstalk Calculator TAB. For critical signals you may be looking to achieve crosstalk coeficient -30dB or lower ( e.g -35dB, -40dB,. see the Table in the next paragraph).</p> <p><i>Picture: Screenshot from Saturn PCB Toolkit -&gt; Crosstalk Calculator TAB</i><br> <a href="http://www.fedevel.com/welldoneblog/wp-content/uploads/2015/10/Saturn-PCB-Toolkit-Crosstalk-Calculator-TAB.png" target="_blank"><img loading="lazy" data-attachment-id="4137" data-permalink="https://welldoneblog.fedevel.com/2015/10/14/how-to-decide-on-minimum-gap-clearance-in-pcb-layout/saturn-pcb-toolkit-crosstalk-calculator-tab/" data-orig-file="https://welldoneblogfedevel.files.wordpress.com/2019/10/b796c-saturn-pcb-toolkit-crosstalk-calculator-tab.png" data-orig-size="977,821" data-comments-opened="1" data-image-meta="{&quot;aperture&quot;:&quot;0&quot;,&quot;credit&quot;:&quot;&quot;,&quot;camera&quot;:&quot;&quot;,&quot;caption&quot;:&quot;&quot;,&quot;created_timestamp&quot;:&quot;0&quot;,&quot;copyright&quot;:&quot;&quot;,&quot;focal_length&quot;:&quot;0&quot;,&quot;iso&quot;:&quot;0&quot;,&quot;shutter_speed&quot;:&quot;0&quot;,&quot;title&quot;:&quot;&quot;,&quot;orientation&quot;:&quot;0&quot;}" data-image-title="Saturn PCB Toolkit â€“ Crosstalk Calculator TAB" data-image-description="" data-image-caption="" data-medium-file="https://welldoneblogfedevel.files.wordpress.com/2019/10/b796c-saturn-pcb-toolkit-crosstalk-calculator-tab.png?w=300" data-large-file="https://welldoneblogfedevel.files.wordpress.com/2019/10/b796c-saturn-pcb-toolkit-crosstalk-calculator-tab.png?w=977" src="https://i0.wp.com/www.fedevel.com/welldoneblog/wp-content/uploads/2015/10/Saturn-PCB-Toolkit-Crosstalk-Calculator-TAB.png" alt="Saturn PCB Toolkit - Crosstalk Calculator TAB" width="977" height="821" class="aligncenter size-full wp-image-4137"></a></p> <p>The table below shows some examples of recommended spacing based on H, where H is dielectricum height between signal layer and reference plane (notice the crosstalk coeficient which in these examples is between -22dB to -35dB):</p> <p><i>Table: Examples of recommended spacing between tracks</i><br> <a href="http://www.fedevel.com/welldoneblog/wp-content/uploads/2015/10/Examples-of-gap-between-tracks-in-PCB-design.png" target="_blank"><img loading="lazy" data-attachment-id="4138" data-permalink="https://welldoneblog.fedevel.com/2015/10/14/how-to-decide-on-minimum-gap-clearance-in-pcb-layout/examples-of-gap-between-tracks-in-pcb-design/" data-orig-file="https://welldoneblogfedevel.files.wordpress.com/2019/10/05482-examples-of-gap-between-tracks-in-pcb-design.png" data-orig-size="1013,642" data-comments-opened="1" data-image-meta="{&quot;aperture&quot;:&quot;0&quot;,&quot;credit&quot;:&quot;&quot;,&quot;camera&quot;:&quot;&quot;,&quot;caption&quot;:&quot;&quot;,&quot;created_timestamp&quot;:&quot;0&quot;,&quot;copyright&quot;:&quot;&quot;,&quot;focal_length&quot;:&quot;0&quot;,&quot;iso&quot;:&quot;0&quot;,&quot;shutter_speed&quot;:&quot;0&quot;,&quot;title&quot;:&quot;&quot;,&quot;orientation&quot;:&quot;0&quot;}" data-image-title="Examples of gap between tracks in PCB design" data-image-description="" data-image-caption="" data-medium-file="https://welldoneblogfedevel.files.wordpress.com/2019/10/05482-examples-of-gap-between-tracks-in-pcb-design.png?w=300" data-large-file="https://welldoneblogfedevel.files.wordpress.com/2019/10/05482-examples-of-gap-between-tracks-in-pcb-design.png?w=1013" src="https://i0.wp.com/www.fedevel.com/welldoneblog/wp-content/uploads/2015/10/Examples-of-gap-between-tracks-in-PCB-design.png" alt="Examples of gap between tracks in PCB design" width="1013" height="642" class="aligncenter size-full wp-image-4138"></a></p> <p>Have a look also at <a href="http://www.fedevel.com/welldoneblog/2015/01/high-speed-pcb-design-rules-lesson-4-of-advanced-pcb-layout/" target="_blank">High Speed PCB Design Rules (Lesson 4 of Advanced PCB Layout)</a> post â€“ especially the <i>Rule 6: Be aware of tracks running in parallel</i>. That may help you.</p> <h2>3) Electrical requirements</h2> <p>If you are designing a board for higher voltage (e.g. 240V), the minimum gap can be calculated and has to follow some rules or meet some requirements. As a good starting point, you can use Saturn PCB Toolkit -&gt; Conductor Spacing TAB. However, it may be more complicated. You may need to consider other factors, for example the environment where the board will be located and also read and study some regulations.</p> <p><i>Picture: Screenshot from Saturn PCB Toolkit -&gt; Conductor Spacing TAB</i><br> <a href="http://www.fedevel.com/welldoneblog/wp-content/uploads/2015/10/Satrun-PCB-Toolkit-Conductor-Spacing-TAB.png" target="_blank"><img loading="lazy" data-attachment-id="4139" data-permalink="https://welldoneblog.fedevel.com/2015/10/14/how-to-decide-on-minimum-gap-clearance-in-pcb-layout/satrun-pcb-toolkit-conductor-spacing-tab/" data-orig-file="https://welldoneblogfedevel.files.wordpress.com/2019/10/3db16-satrun-pcb-toolkit-conductor-spacing-tab.png" data-orig-size="977,821" data-comments-opened="1" data-image-meta="{&quot;aperture&quot;:&quot;0&quot;,&quot;credit&quot;:&quot;&quot;,&quot;camera&quot;:&quot;&quot;,&quot;caption&quot;:&quot;&quot;,&quot;created_timestamp&quot;:&quot;0&quot;,&quot;copyright&quot;:&quot;&quot;,&quot;focal_length&quot;:&quot;0&quot;,&quot;iso&quot;:&quot;0&quot;,&quot;shutter_speed&quot;:&quot;0&quot;,&quot;title&quot;:&quot;&quot;,&quot;orientation&quot;:&quot;0&quot;}" data-image-title="Satrun PCB Toolkit â€“ Conductor Spacing TAB" data-image-description="" data-image-caption="" data-medium-file="https://welldoneblogfedevel.files.wordpress.com/2019/10/3db16-satrun-pcb-toolkit-conductor-spacing-tab.png?w=300" data-large-file="https://welldoneblogfedevel.files.wordpress.com/2019/10/3db16-satrun-pcb-toolkit-conductor-spacing-tab.png?w=977" src="https://i0.wp.com/www.fedevel.com/welldoneblog/wp-content/uploads/2015/10/Satrun-PCB-Toolkit-Conductor-Spacing-TAB.png" alt="Satrun PCB Toolkit - Conductor Spacing TAB" width="977" height="821" class="aligncenter size-full wp-image-4139"></a></p> </div>

How to decide on Minimum Gap / Clearance in PCB Layout

<div class="entry-content"> <p>It would not be possible without you! Thank you for all your support, comments and feedback. If you would like to see what is behind the scene (where I record the videos), have a look:</p> <div class="jetpack-video-wrapper"><span class="embed-youtube" style="text-align:center; display: block;"><iframe class="youtube-player" src="https://www.youtube.com/embed/Ahhc425ako0?version=3&amp;rel=0&amp;showsearch=0&amp;showinfo=1&amp;iv_load_policy=1&amp;fs=1&amp;hl=en&amp;autohide=2&amp;wmode=transparent" allowfullscreen="true" style="border: 0px; display: block; margin: 0px; width: 640px; height: 360px;" sandbox="allow-scripts allow-same-origin allow-popups allow-presentation" data-ratio="0.5625" data-width="640" data-height="360"></iframe></span></div> </div>

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