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, 09-15-2026, 08:03 PM

🤖 In the meantime, here’s a response from the [FEDEVEL AI HW Assistant]().
It helps to find relevant resources for your question, but it may make mistakes as it’s still in early development.

This is the response from the AI Assistant:
The issue you're experiencing with XSignals combining nets in Altium's fly-by topology setup is partially addressed in our training materials. Here's what you need to know:

1. **Net Naming Requirement**:
Ensure your DDR_A10 net is explicitly named at both connection points (memory module 1 and 2). Altium's XSignals wizard relies on clear net identification. As shown in [this video about net naming](https://www.youtube.com/watch?v=Hx4RH1hZCGQ&t=1), even simple connections between two pins should have explicit net labels to avoid ambiguity during layout.

2. **Manual XSignal Creation**:
When the wizard fails:
- Right-click between the driver (controller) and receiver (memory module 1)
- Select "Create XSignals Between Components"
- Repeat for module 1 to module 2 connection
This manual approach helps when automatic detection fails, as demonstrated in [our XSignals tutorial](https://www.youtube.com/watch?v=jpk-hfsFaqA&t=634)

3. **Segment-Specific Rules**:
For fly-by topologies, you need separate rules for:
- Controller to first memory
- Memory-to-memory segments
- Entire controller-to-last-memory path
The system automatically creates these when properly configured, as shown in [this layout example](https://www.youtube.com/watch?v=jpk-hfsFaqA&t=1962)

4.

, 09-15-2026, 08:03 PM

**Common Pitfalls**:
- **Unnamed intermediate nets**: All T-junction points in fly-by routing must have explicit net names
- **Component designators**: Verify memory modules have unique designators (U1, U2, etc.)
- **Schematic connectivity**: Use ports/power symbols instead of implicit connections

If the issue persists after checking these points, you might need to manually create matched length rules using the PCB panel's "From-To Editor" as a temporary workaround. The video materials show this as a fallback method when automatic XSignal detection struggles with complex topologies.

You can continue chatting with the AI Assistant here:
https://fedevel.com/hw-assistant