TSSOP SDRAM layout guideline
, 12-17-2023, 01:27 PM
Dear Robert,First of all thanks for amazing courses, I remember it was great. I've finished advanced PCB layout course about 4 years ago, and only now I have some chance to use it.I'm thinking to utilize W9825G6KH-6 (https://www.digikey.com/en/products/detail/winbond-electronics/W9825G6KH-6/5001919) 256Mbit SDRAM chip. I don't need much and I want to do it on cheap 4layer PCB. First, can somebody suggest if there layout guidelines for that type of memory (I usually see DDR2 minimum)?And what layers are preferred? I had a plan to use default JLCPCB stackup, In that case ideally I have top and bottom layers GND (above and beneath the signals) and route RAM signals on the inner layers, right?Sorry if these are dumb questions, I have nobody to ask here in Kazakhstan.
Robert Feranec , 12-18-2023, 07:24 AM
I usually use 3313 stackup. For 4 layer stackup I often try to keep the two inner layers GND, if not possible I make one of them power and the other one GND (but then you may need to be careful about using stitching capacitors to "connect" these two layers together). I then route all the signals (+ powers) on top and bottom layers. Also, this looks like up to 200MHz memory, it should not be very sensitive to tight length matching. But if you would like to get at least some guidlines, you can search for "design guidlines sdram" e.g. https://www.issi.com/WW/pdf/IS43DR00-001.AN.pdf or https://www.nxp.com/docs/en/application-note/AN2826.pdf
, 12-18-2023, 07:45 AM
Thanks for you answer!I remember from the course you told that using outer layers is often a last resort, but is it more for very high speed stuff and more than 4 layers?
Robert Feranec , 12-18-2023, 07:55 AM
for 4 layer pcb there are not really many options. This video may help: https://youtu.be/kdCJxdR7L_I?si=kHINkLjeyyxYnOdN
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