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HasanTheSyrian_ , 03-25-2026, 12:03 PM

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HasanTheSyrian_ , 03-25-2026, 12:05 PM

Hello, I have routed MIPI clock as the following with the clock diff pair having 2 via pairs (4 vias) at the beginning (and 2 pairs at the end). I cant route to the left because the diff pairs need to switch polarity:

HasanTheSyrian_ , 03-25-2026, 12:05 PM

HasanTheSyrian_ , 03-25-2026, 12:07 PM

Im wondering if moving the MIPI connector to the left and routing CLK next to the signal would be better in terms of signal integrity like this. Maybe with gnd vias in between. Im wondering if the I2C/GPIO/3V3 pins on the left of the clk trace will have a negative impact too.

HasanTheSyrian_ , 03-25-2026, 12:08 PM

HasanTheSyrian_ , 03-25-2026, 12:09 PM

HasanTheSyrian_ , 03-25-2026, 12:14 PM

QDrives , 03-25-2026, 03:13 PM

If the I2C/GPIO/3V3 would have a negative impact (they do, but big enough...?) then all routing options shown will have such impact.

HasanTheSyrian_ , 03-25-2026, 06:58 PM

how do all options have the same impact

QDrives , 03-25-2026, 11:40 PM

Not the same, but will have some impact.
See the most recent video from Robert: https://www.youtube.com/watch?v=iZChE0CRpE4

HasanTheSyrian_ , 03-26-2026, 12:09 PM

how would you route it? do i keep the ground vias in between?

HasanTheSyrian_ , 03-26-2026, 01:34 PM

this is what i have done so far

Gobi , 03-26-2026, 02:35 PM

Generally to avoid coupling from the neighbour line, 2x or 3x width of the trace spacing can be provided.

HasanTheSyrian_ , 03-26-2026, 11:39 PM

theyre apart

HasanTheSyrian_ , 03-26-2026, 11:39 PM

do i keep the gnd vias?

QDrives , 03-27-2026, 10:31 PM

I might route the same as you do.
It all depends on the speed (edge rate) and there is only so much you can do...

HasanTheSyrian_ , 03-28-2026, 06:25 PM

you mean with the vias?

QDrives , 03-28-2026, 07:59 PM

I do not know exactly which vias you mean?
Often, a guard ring does not reduce crosstalk more than the same spacing between the traces alone would create.