FEDEVEL
Platform forum

Chef Jeff , 08-08-2025, 05:41 PM

Stack up fr4:
1. Signal
2. Gnd
3. Signal
4. Pwr
5. Gnd
6. Signal

If I am routing the diff pairs for lvds on layer 3. do I calculate them as microstrip or stripline. Where the power plane will not be a solid fill their will be cuts and such so lvds signals should not couple to layer 4 too much which makes me think I need to calculate the lvds 100ohm impedance of the traces to be microstrip. What are y’all’s thoughts on this?

Robert Feranec , 08-12-2025, 05:49 AM

I had the same question as you, so what I did I placed one GND plane close to the signal layer, one GND plane further and I found out, if the second plane is far away it has minimum influence. So when I am in this situation I use stripline calculations but I place the solid gnd plane close to the signal layer and the power planes far away from the signal layer. I may do some simulations about this, that could be interesting

QDrives , 08-12-2025, 11:47 AM

You want something like 2 times 3 layer board. So the dielectric between 2 and 3 is small (<= 0.2mm) and the distance between 3 and 4 is relative large (>= 0.6mm).
But do you need a power layer to begin with?

Chef Jeff , 08-12-2025, 06:46 PM

Do I need a power layer probably not actually some signals will most likely be on the power layer nothing high speed though. I have an fpga, ddr3, usb3, high speed dac and adc so I do want low impedance power planes with large enough areas so I don’t need to dealing with esl and esr ect. Still working on schematics so no rush on the pcb side just yet as nothing is finalized but I am doing component placement and mapping things out in my head.