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Omar Hamila , 11-26-2025, 04:15 PM

Hi!
I’m currently working on a board design based on the Microchip PolarFire SoC MPFS025T-FCVG484, and I’m trying to run signal-integrity simulations in HyperLynx for the LPDDR4, GPIOs (Bank 1), HSIO (Bank 0), and XCVR interfaces. I’m running into several issues:

-the IBIS models from Microchip only include the I/O standards so I choose the right standard myself based on what standard I'm using, so is this the right way to do or I have to generate or configure the IBIS model myself and include the real pin numbers?

-When running SERDES simulations on the XCVR channels, many S-parameters fail to solve when using “Analyze 3D EM.”

-I’m not sure how to properly set up these simulations, and I still do not have a clear method for running proper simulations on the GPIO and HSIO pins.

-I tried generating and configuring the Microprocessor Subsystem with MSS configurator and generating the IBIS model with Libero SoC myself to simulate the LPDDR4 interface and run the DDR batch simulation, but I keep getting an IBIS-related error and I’m unable to load the ODT models, even though Microchip support told me that the IBIS file is correct (you can find the ibis model below).

If you have any resources, explanations, or guidance that could help me work through these issues, I would greatly appreciate it. Thanks!