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Kulunu , 07-29-2018, 04:13 AM

Hi All,

I'm interested in studying and understanding DDR memory calibration, DDR stress testing & DDR Layout fault isolation for custom hardware designs.

Presently I have a little knowledge with NXP calibration and stress testing tools related to i.MX6Q processor, DDR layout designing (Fly by topology, T topology), Linux based Stress app tester, KOZIO Calibration tools and etc.

I wish to expand my knowledge on this areas and searching for some publications and research papers related to above stuffs for my studies and usage.

Could you please suggest me few research papers or publications (Topics) on this area and the future research opennings related to this areas ?

I must be thankful to you if you will kindly reply me soon.

Regards,
Kulunu.

robertferanec , 07-30-2018, 11:59 AM

Maybe check out this document: https://www.nxp.com/docs/en/application-note/AN4467.pdf
Also, I learned some info from documentation included in the iMX6 DDR Stress Test Tool: https://community.nxp.com/docs/DOC-96412