Platform forum

Length Match & Memory Fan out

meet , 08-14-2017, 07:50 AM
Dear Robert,
I have studying the second Lesson for advance course and i hvae below queries.
1. Does we need to match the length among data byte group? for example Data byte group 1 length is 1 inch and data byte group length is 1.5 inch and clock length is 2 Inch. in presetation i have noticed that data group should be less than Max clock length and 15 mil tolerance is allowed in group signals.

2. for lesson 2, at 1.30Hrs, it is mentioned to use micro via for one memory and through hole for bottom layer memory. in case of through hole there would be a stub, as we will be using layer 10 for layout. so there would be a stub.. i might be wrong to understand. could you please make it clear. i have highlighted in green color.

3. Could you please suggest, while doing placement of Decoupling under BGA, which power net should have priority. For example we have +1V375_VDDSOC_IN, +1V375, +1V5_DDR, +3V3, +1V1_VDDSOC_CAP, +1V2_VDD_ARM_CAP, +DDR_VREF.

I found many supplies on sheet 18 15 and 04.
please guide how to make selection for their decoupling capacitor placement . or If their is some document, please refer.
robertferanec , 08-15-2017, 02:29 PM
1) "Data byte group 1 length is 1 inch and data byte group length is 1.5 inch"
- I am not really sure what you mean

2) This may help you: http://www.fedevel.com/designhelp/fo...dr3-lpddr-ddr3

3) Try to place all the capacitors as close as you can to the pins. They are all important, however the capacitors with lowest values are generally the capacitors which are placed closest to the pins. Have a look at our design, it can give you some ideas. Also, they do write about decoupling in the iMX6 Design Guide, however I think they use smaller size caps.
meet , 08-15-2017, 11:06 PM
Thanks Robert, for your quick reply.
" for query 1: is there any relationship, in terms of length matching between the data groups. for example, data group signal should be having 25/50/30 mil length tolerance among the group.
Another example like, data grp 1 is 1400 mil data grp 2 is 1500 mil datat grp 3 is 1450 mil, and data grp 4 is 1550 and clock length is 1600. so is this acceptable? or we need to match the length among group. for example all data group could be withing 25 mil tolerance?
robertferanec , 08-17-2017, 10:40 AM
1) In some design guides you will find that requirement ... e.g. it may be about maximum difference between the shortest and longest group. If it is required, you would find it in the design guide.

Otherwise, you should be just fine. If possible I try to do the placement the way, that CPU is in the middle between chips, so the difference between group length is as small as possible. I had a board, where I had to place CPU close to MEM1 chip (so the length of MEM1 group was very short and length of data signals routed to MEM4 chip was very long) and it was on the edge of the maximum allowed tolerance difference between the groups.
meet , 08-17-2017, 11:33 PM
Thanks Robert, i appreciate your detailed replies....for sure, it is adding more learning to me.
meet , 12-19-2017, 06:42 AM
Hello Robert,
Hope, you are doing good and will be busy for X-Mas Shopping. i wish you Happy Cristmas in Advance.

I was working for Lesson 2 and had a query for Clock Routing (CLK1, CLK0)
Please see the attached snap shot. The left side snap shot is the Clock routing done by me on TOP Layer, while right side snap shot is PCB of your training material..

May i kindly know, why you didnt routed the clock signal on top (As done By Me) instead of routing TOP-to Layer10 and then Memories.

I found the space in top Layer to route clocks and no need to route in layer 10... could you please if their is any disadvantage or drawbacks.

I have matched the length of clocks too (33.572)
robertferanec , 12-19-2017, 10:22 AM
I wanted to route the last branch from middle, so the TOP and BOTTOM memory chips are both routed through VIA (the connection to the chips are more similar when routed this way). I didn't want to connect the TOP chip directly and bottom chip through VIAs (the signals would be routed little bit different - BOTTOM memories would have 1 VIA more than the TOP chips). Maybe if you simulate it, it would be fine, but routing inside to PCB and then out was easier than relying on simulation results. I hope this helps.

Merry Christmas
meet , 12-20-2017, 12:17 AM
Thank you Robert for suggestion and wishes as well.

I understood the answer and role of Via, for bottom memory. I have one more doubt about the length of Branch connection.

Does this track length of branch connection, is a part of total clock net length?
in other words, what would be the total length for clock? With or Without Branch connection?

robertferanec , 12-20-2017, 09:59 AM
The total length of the signal (sum of all segments of this track) is not relevant. You measure pin to pin distance (e.g. distance from CPU pin to TOP memory pin). Have a look at this video: https://www.fedevel.com/welldoneblog...useful-things/
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