+DDR_VREF Routing
meet , 01-25-2017, 02:22 AM
Hello Feranec,
I am opted the course IMX rex module. i found (as shown in snapshot), that the signal +DDR_ VREF is routed by thick traces on layer 5.
May i kindly know that, why didn't we poured a continuous plane for this signal.
Could we do this, if not than what is the reason behind it.
I am opted the course IMX rex module. i found (as shown in snapshot), that the signal +DDR_ VREF is routed by thick traces on layer 5.
May i kindly know that, why didn't we poured a continuous plane for this signal.
Could we do this, if not than what is the reason behind it.
robertferanec , 01-25-2017, 09:15 AM
We didn't want to make it a plane as it is very sensitive voltage and we didn't want it to pick up noise from the neighbor layers. The currents are small, so we decided to use a star connection instead.
nachodizz990 , 02-24-2017, 03:06 PM
As Robert said,
This is not a power plane and this is not a power path, this is a low current reference voltage for the center of the eye mask and supplies the ddr comparators you only want to have a clean signal with low IR drop ( 20-25 mils)
For power planes ( processor domains , high current) you want wide planes to sattisfy ZTarget and IR drop
I calculate Ztarget as follows:
I take the processor 1.1V voltage domain at Drystone test.
Lets say 3A.
The processor supplier tells you 3% tolerance, this is 33 mV
Ztarget is: 0.033/(0.5x3A)= 0.033/1.5= 0.022 ohm for the entire plane and all the freqcuency range, this is why youbfind some parallel capacitos of different values to reduce esr to ztarget accross all frecuencies up to 200 mhz. Then power- ground capacitance above 200 mhz and for VHF, the internal soc caps (discrete or morfet based)
Some times you only need to decouple low wideband impedsnce up to 200 mhz because the SOC has internal caps)
Other reference designs include the same value for all caps ( 220nf) i have te explanation but its hard to xplain i have a doccument about this, i will search it)
I suggest you to copy Robert and Fedevel Layout behaviours, i've learned from Fedevel and i complemented Fedevel Lessons with some especialized PDN books.
This is not a power plane and this is not a power path, this is a low current reference voltage for the center of the eye mask and supplies the ddr comparators you only want to have a clean signal with low IR drop ( 20-25 mils)
For power planes ( processor domains , high current) you want wide planes to sattisfy ZTarget and IR drop
I calculate Ztarget as follows:
I take the processor 1.1V voltage domain at Drystone test.
Lets say 3A.
The processor supplier tells you 3% tolerance, this is 33 mV
Ztarget is: 0.033/(0.5x3A)= 0.033/1.5= 0.022 ohm for the entire plane and all the freqcuency range, this is why youbfind some parallel capacitos of different values to reduce esr to ztarget accross all frecuencies up to 200 mhz. Then power- ground capacitance above 200 mhz and for VHF, the internal soc caps (discrete or morfet based)
Some times you only need to decouple low wideband impedsnce up to 200 mhz because the SOC has internal caps)
Other reference designs include the same value for all caps ( 220nf) i have te explanation but its hard to xplain i have a doccument about this, i will search it)
I suggest you to copy Robert and Fedevel Layout behaviours, i've learned from Fedevel and i complemented Fedevel Lessons with some especialized PDN books.
nachodizz990 , 02-24-2017, 04:49 PM
Im sorry i forgetted an important point, how to know how PDN impedance profile do you have?
Place dummy decoupling caps footprints, get a VNA, (coppermountaintech,compact VNAs) and make real measerements at vcc pins.
Place dummy decoupling caps footprints, get a VNA, (coppermountaintech,compact VNAs) and make real measerements at vcc pins.
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