Hi all, i want to share with you a little tip about DDR3 electrical lenght tuning.
This is an usefull tip because if you donÂ´t realize on such a thing, your design will go probably directly to the trash.
Supose you are escaping a trace from a processor BGA ball (Layer 1), now the trace will go trough a via from Layer 1 to layer 3 and then will pass again trough a via to layer 1 and finally to a DDR3 chip ball.
Okay, now you do the same thing on an entire byte lane and Altium says that all the signals of the byte lane have the same "physical" lenght.
You know that if you routed your signals the same way, L1 (Processor)) - L3 - L1 (Memory Chip) the signals will also have the same electrical lenght, itÂ´s true! (If your chip provider says that the internal chip lenghts are the same)
Now you assigned a 10 mil tolerance (or 10 ps) between all the byte lane signals and you may think that youÂ´re ok
LetÂ´s show a terrible exception.
The red marked signal flows more distance trough Layer 1 and you know that external signals propagate faster than internal signals.
The propagation time of the blue marked signal is 215 ps and 187ps for the red marked signal, so youÂ´re by far out of the 10 ps tolerance.
Now you have to place an exception to that signal in the group and you will need to make it longer to compensate this situation.
For accurate measurements, you hace to place on Hyperlynx your entire stackup and configure the nets the same way that your traces are in your design.
I hope this helps !!