TIP on DDR3 electrical lenght tuning
nachodizz990 , 08-16-2016, 12:14 PM
Hi all, i want to share with you a little tip about DDR3 electrical lenght tuning.
This is an usefull tip because if you don´t realize on such a thing, your design will go probably directly to the trash.
Supose you are escaping a trace from a processor BGA ball (Layer 1), now the trace will go trough a via from Layer 1 to layer 3 and then will pass again trough a via to layer 1 and finally to a DDR3 chip ball.
Okay, now you do the same thing on an entire byte lane and Altium says that all the signals of the byte lane have the same "physical" lenght.
You know that if you routed your signals the same way, L1 (Processor)) - L3 - L1 (Memory Chip) the signals will also have the same electrical lenght, it´s true! (If your chip provider says that the internal chip lenghts are the same)
Now you assigned a 10 mil tolerance (or 10 ps) between all the byte lane signals and you may think that you´re ok
Let´s show a terrible exception.
The red marked signal flows more distance trough Layer 1 and you know that external signals propagate faster than internal signals.
The propagation time of the blue marked signal is 215 ps and 187ps for the red marked signal, so you´re by far out of the 10 ps tolerance.
Now you have to place an exception to that signal in the group and you will need to make it longer to compensate this situation.
For accurate measurements, you hace to place on Hyperlynx your entire stackup and configure the nets the same way that your traces are in your design.
I hope this helps !!
This is an usefull tip because if you don´t realize on such a thing, your design will go probably directly to the trash.
Supose you are escaping a trace from a processor BGA ball (Layer 1), now the trace will go trough a via from Layer 1 to layer 3 and then will pass again trough a via to layer 1 and finally to a DDR3 chip ball.
Okay, now you do the same thing on an entire byte lane and Altium says that all the signals of the byte lane have the same "physical" lenght.
You know that if you routed your signals the same way, L1 (Processor)) - L3 - L1 (Memory Chip) the signals will also have the same electrical lenght, it´s true! (If your chip provider says that the internal chip lenghts are the same)
Now you assigned a 10 mil tolerance (or 10 ps) between all the byte lane signals and you may think that you´re ok
Let´s show a terrible exception.
The red marked signal flows more distance trough Layer 1 and you know that external signals propagate faster than internal signals.
The propagation time of the blue marked signal is 215 ps and 187ps for the red marked signal, so you´re by far out of the 10 ps tolerance.
Now you have to place an exception to that signal in the group and you will need to make it longer to compensate this situation.
For accurate measurements, you hace to place on Hyperlynx your entire stackup and configure the nets the same way that your traces are in your design.
I hope this helps !!
mairomaster , 08-16-2016, 02:19 PM
Very good tip and an example! I am even surprised that the difference is so big. It will probably still be fine in your case, but it is something to be aware of for sure.
nachodizz990 , 08-16-2016, 02:20 PM
Hi ! Mairomaster 
in my case it´s a disaster, the diference it´s greater than the 10ps tolerance, how can manage this situation with altium?
I mean that i have to make clear annotations explaining why a signal inside a group it´s much larger than the rest for compensate the diference
Altium should include some options for manage this situations !!
Maybe @robertferanec have some trick to organize this exceptions
I´m writing a word documment to explain this differences
in my case it´s a disaster, the diference it´s greater than the 10ps tolerance, how can manage this situation with altium?I mean that i have to make clear annotations explaining why a signal inside a group it´s much larger than the rest for compensate the diference
Altium should include some options for manage this situations !!
Maybe @robertferanec have some trick to organize this exceptions
I´m writing a word documment to explain this differences
robertferanec , 08-16-2016, 02:25 PM
In reality, for standard DDR3 memory layout it's not so strict (or to say it in other words, some of the rules are too strict). You have some space to breakout the CPU and memory chips. For example in some design guides they tell you to keep the length of breakout part (the part of the track from pad to the first VIA) within 100mil, in some designs they will tell you to keep it under 1inch, ... depends on the interface and speed). Of course, try to keep the difference routed on TOP/BOTTOM layer similar between the signals in one group, but the length doesn't have to be exactly the same - and in reality it never is. In many cases it would be impossible to try to keep TOP and BOTTOM length exactly the same in all signals within one group. Tested in many designs, works oki.
nachodizz990 , 08-16-2016, 02:31 PM
Thank you @robertferanec, but i mean that the signal doesnt go trought Bottom, it only goes trough L1 (external) and L3 (Internal so slower) and the simulations yeld me this numbers
nachodizz990 , 08-16-2016, 04:49 PM
@roberferanec, FINALLY I WILL follow your suggestion and i will make it equal, because i think hyperlynx it´s making some strange ( it´s a lot of difference)
mairomaster , 08-17-2016, 01:53 AM
Yeah something might be dodgy with the simulation when I think about it now. I did some quick estimation of what the difference would normally be.
According to Saturn, the propagation speed for some standard high speed board will be:
Top/Bottom: 5.5 ps/mm
Internal: 6.8 ps/mm
So in order to have 10 ps difference, you should have about 8 mm longer track on the top layer with one of the signals. I don't remember what the tolerance for DDR3 needs to be exactly, but if we have it running at 1600 GT/s the period will be 625 ps. If we are conservative and use even 1/10th of that, this will be 60 ps tolerance. So you can easily have 50 mm longer track (could be the entire signal) on the top layer and things will still be ok. That also shows how conservative we are normally with length matching
According to Saturn, the propagation speed for some standard high speed board will be:
Top/Bottom: 5.5 ps/mm
Internal: 6.8 ps/mm
So in order to have 10 ps difference, you should have about 8 mm longer track on the top layer with one of the signals. I don't remember what the tolerance for DDR3 needs to be exactly, but if we have it running at 1600 GT/s the period will be 625 ps. If we are conservative and use even 1/10th of that, this will be 60 ps tolerance. So you can easily have 50 mm longer track (could be the entire signal) on the top layer and things will still be ok. That also shows how conservative we are normally with length matching
alazareff , 08-19-2016, 09:43 AM
Hello,
Interesting topic
I have found the same order of magnitude with this formula, which helps to understand the physics behind :
V = C / square(Er)
C = speed of light
Er = dielectric constant
It is basically the same method as Saturn propagation speed formula i think.
I also attached a brief comparison of DDR3 requirement for 2 FPGA vendors and IMX6. The funny thing is that Xilinx provides timing informations, while Altera and Freescale provides length tolerances information. This comparison was done a year ago, so maybe an update is necessary.
So basically, for DDR3, a 2mm difference on one layer should be ok, as soon as the entire net meets the requirement.
Interesting topic
I have found the same order of magnitude with this formula, which helps to understand the physics behind :
V = C / square(Er)
C = speed of light
Er = dielectric constant
It is basically the same method as Saturn propagation speed formula i think.
I also attached a brief comparison of DDR3 requirement for 2 FPGA vendors and IMX6. The funny thing is that Xilinx provides timing informations, while Altera and Freescale provides length tolerances information. This comparison was done a year ago, so maybe an update is necessary.
So basically, for DDR3, a 2mm difference on one layer should be ok, as soon as the entire net meets the requirement.
mairomaster , 08-19-2016, 10:36 AM
I wonder why the iMX6 requirements are so tight compared to the others, it doesn't really make sense. Could it be that the length matching in the chip itself is not that great (being close to the limit) and you have to compensate with the length matching on the board?
alazareff , 08-19-2016, 10:53 AM
That is funny, i was wondering why Altera has a much wider tolerance 
But i think it depends on many factor like the DDR3 controller inside the chip, the signal integrity inside the chip, length matching inside the chip.....
It can also be quality requirement difference between IC vendors.
But i think it depends on many factor like the DDR3 controller inside the chip, the signal integrity inside the chip, length matching inside the chip.....
It can also be quality requirement difference between IC vendors.
robertferanec , 08-19-2016, 11:24 AM
@alazareff what is the frequency of each memory interface?
alazareff , 08-19-2016, 12:20 PM
For Altera Cyclone V, the max is 400MHz
For the Xilinx Zync, it is 444MHz for the -3 grade
And for the IMX6 it is 400MHz
For the Xilinx Zync, it is 444MHz for the -3 grade
And for the IMX6 it is 400MHz
robertferanec , 08-19-2016, 01:13 PM
Are you using SOLO iMX6? The QUAD iMX6 DDR3 runs at 533MHz.
alazareff , 08-19-2016, 01:25 PM
automotive grade
Does it mean that Freescale requirement for the length matching could be reduce with 400MHz DDR3 ?
Does it mean that Freescale requirement for the length matching could be reduce with 400MHz DDR3 ?
robertferanec , 08-23-2016, 07:00 AM
I am not sure if I would "reduce" DDR3 length matching requirements. Once we are doing length matching it's not so difficult to do it as close as possible. It's not really more work or much more time.
Use our interactive Discord forum to reply or ask new questions.