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About the video between Robert Feranec and Rick Hartley about stackups

mulfycrowh , 07-04-2023, 01:45 PM
Hi everyone and more particularly Robert,

A 12 layers stackup is presented:


If top and bottom layers have Sig/Pwr architecture, how do you manage the placement of shielding vias around tracks and differential pairs?

mulfycrowh , 07-06-2023, 11:35 AM
Any idea maybe?
qdrives , 07-06-2023, 02:41 PM
Are you talking a via stitching a guard ring?
What would be the problem with that compared to Sig/Pwr on the outer layers?
mulfycrowh , 07-06-2023, 02:52 PM
The attached screenshot shows shielding vias on the bottom layer filled with polygon pour linked to GND (here H0_CLK_SHIELD).
If bottom layer has a Sig/Pwr architecture, it means that it is filled with polygon pour linked to Pwr.
In that case, the vias are no more connected with the polygon pour.
Is it a problem?
qdrives , 07-07-2023, 01:35 PM
Sig/Pwr means that power is routed on that layer, not so much that it is filled with power.

Out of curiosity, why the guard trace? Alternatively, why not a stripline?
Reason for me asking is that I have seen multiple videos now where they explain that a guard trace has almost no effect.
mulfycrowh , 07-07-2023, 01:49 PM
Do you mean that on that layer Sig/Pwr, the main polygon pour is GND?
qdrives , 07-08-2023, 07:42 AM
How much Gnd pour can you get on the outer layers?
If you want Gnd to be used for shielding, guard ring or a coplanar waveguide, you need Gnd. How you flood the remaining space is up to you.
robertferanec , 07-11-2023, 04:32 PM
I almost never route signals like that (guarding tracks, power pour, gnd pour). Ideally I prefer to have two solid GND planes above and below signal layer, if not possible, at least one solid GND plane placed close to the signal layer (100um or less). With guarding tracks it may be hard to calculate impedance. If I use mixed layers (signal / power) then power is designed as specific power polygons, not a copper pour.
mulfycrowh , 07-11-2023, 04:49 PM
@robertferanecRobert, did you have a screenshot to illustrate what you are saying.
I use shielding vias and gnd/pwr pours with of course gnd planes.
If you don’t use shielding vias, the current will spread everywhere.
I don’t use guarding tracks.
What you see is a small polygon pour between tracks.
robertferanec , 07-12-2023, 02:15 AM
@mulfycrowh what signals are you trying to shield? Just the clock? Don't forget, return currents for higher frequencies will travel under the signals if solid gnd is used on neighbor layer.
mulfycrowh , 07-12-2023, 02:38 AM
@robertferanec I usually protect every signal: the problem is I meet issues to route power.
I have always GND plane and sometimes both of them, above and below.
qdrives , 07-12-2023, 01:54 PM
"Protect" -- from what?
Recently I have many videos about cross talk. Like this one: https://www.youtube.com/watch?v=grjvwLWDYfU
Or this blog: https://www.signalintegrityjournal.c...-or-leave-them
qdrives , 07-12-2023, 01:58 PM
then power is designed as specific power polygons, not a copper pour.
With "copper pour" do you mean over the entire board and with "polygons" just specific 'traces'?
robertferanec , 07-23-2023, 04:06 PM
I recommend to watch my videos with Eric Bogatin and Rick Hartley. This will help you to imagine what is happening around tracks. I am not sure what you mean by "protecting every signal", but if we are talking about PCB layout, if stackup is good (e.g. solid GND plane close to the signal layer, stitching vias, ...), noise around the signals will stay very close to tracks and will not spread around the board.

For power delivery, watch my videos with Rich Hartley, Steve Sandler and Eric Bogatin. Important is placement, stackup and decoupling. Again, if its done properly, no need to "protect signals".

What specific problems you have in what exact situation and in what specific pcb layout?
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