I'm in the middle of motherboard bring-up that has Intel Tiger Lake UP3 CPU.
Seems like I had a good run so far at power-up sequence. here is a list of all power rails \ signals that I already checked and validated that they are HIGH:
![](https://preview.redd.it/s55qm5ccvm391.png?width=817&format=png&auto=webp&s=b53e2e63cdba5b7e1d1138b4ca365de180d4eaaf)
as you see, I still can't get SLP_S5# = High, which means I'm still at the sleep state.
Note 1: power-up sequence is controlled by an FPGA.
Note 2: SLP_S0# is connected to 100K PU according to INTEL Platform Design Guide, as opposed to INTEL Validation board that has 100K pull down.I pulled SLP_S0# low from FPGA (now it’s on ~500mv voltage). This change Still didn’t get me to SLP_S5# = HIGH.
Note 3: I flashed BIOS Binary to BIOS-SPI FLASH AND seems like the SoC is trying to communicate with the SPI Flash but the SoC is not proceeding to higher states:
SPI_SI_FL (SPI_MOSI)
![](https://preview.redd.it/tuyh8h6fvm391.png?width=625&format=png&auto=webp&s=d2824959435775871294e20b43549e6a78070e6d)
SPI_SO_FL (SPI_MISO)
![](https://preview.redd.it/mtn0ubbgvm391.png?width=625&format=png&auto=webp&s=81d72f53116d35c4e1b09c6f7618090b48dd1f34)
SPI_CLK_FL (SPI_CLK)
![](https://preview.redd.it/xdmln39hvm391.png?width=625&format=png&auto=webp&s=53681602868bdcb83873a59fe24df05c7cbbe902)
SPI_CLK_FL (SPI_CLK) – R367 (ZOOM IN)
![](https://preview.redd.it/ni0gdinivm391.png?width=625&format=png&auto=webp&s=c6358bd383e78ecbae7251bc7cabfa8097b6c8e1)
here is a
schematic for my motherboard for those who have Dropbox account.
I would like to get some debug ideas that could help checking the source of the problem