# FEDEVELPlatform forum

## return current of low voltage low frequency signal.

znp2015 , 07-19-2021, 02:13 PM
Hi,

I have seen many youtube videos of the current return path from FEDEVEL academy that shows how the return current of high frequency and low frequency are. But in all of them, the current is high enough, for example, 1-10 A, to simulate and show the current flow. In this regard, I am really interested in answering these two questions:

1) different types of return paths: reference to power, reference to GND. for example, consider that we have an LED that one the side is connected to VCC and the other side connect to the LED1_DRIVING_PIN. In this condition, what is the return path? Is that the power plane is the return path? Is that the putting power plane is working as a return path. Then the current goes to GND through decoupling capacitors? or consider that we have Photo Diodes connected to PDREF and ADC_INPUT. is that the return current of Photo Diodes is PDREF? Putting PDREF is working or not? We do not have a decoupling capacitor on PDREF. So the return current is inside the IC?

2) about the current value. Consider that the current for Photo Diodes is about 100nA-50uA. What happened about the signal integrity of such this signal? We should be concerned about the cross-talk of another part of this signal, or we should have specific consideration about the return path.

In the end, working with the simulator is so difficult, and in many cases, the results are not as in the real. But if we can see some practical topics in case of mixed-signal systems with low frequency and low voltage and digital part and other hands with some power signals, such as some nice discussion of FEDEVEL that is really expert on describing, is valuable.

Thank you so much.

Best Regards,
Mostafa
robertferanec , 07-20-2021, 05:12 AM
I could simulate that, it could be interesting. I am making a note about it.

PS: in simulations I used higher currents, but I would expect to see the similar results for lower currents. I would say, the scale would change and I would expect some details to be a little bit different (e.g. maybe currents only flowing on neighbour layers?), but generally I would expect the results to be similar. But, I may be surprised.
znp2015 , 07-20-2021, 08:50 AM
Hi Robert,
when the current goes to mA and uA and on the other hand, the PD frequency is about 1 Hz. I really can not understand the return current, because the current and frequency are not as much as that can goes between layers due to capacitive induction.

that is really good. especially in HDI that the layers are so close to each other. it is really valuable to see the effect of the signal on each other.
I have seen the crosstalk of the digital signal with 400 KHz (I do not know di/dt) on the Photodiode signal.

By the way, thank you so much for your valuable information.

Best Regards,
Mostafa
qdrives , 07-21-2021, 06:17 PM
Return path video are with Eric Bogatin. Layer stackup and return path via power is with Rick Hartley (at least in his course).
If a signal is referencing a power plane: https://www.youtube.com/watch?v=ySuUZEjARPY&t=3736s
Signal integrity and cross talk is more for high speed (rising edge). Current / voltage less so.

"I have seen the crosstalk of the digital signal with 400 KHz (I do not know di/dt) on the Photodiode signal."
How about line length and termination?
IBIS models can help with rise time.

@robertferanec In your simulation we could see that the 'signal' was also visible a few layers lower. Could it be that the current you used (10A?) was more than the skin depth of the refence plane?
robertferanec , 07-22-2021, 04:09 AM
when the current goes to mA and uA and on the other hand, the PD frequency is about 1 Hz
- I don't think it will simulate 1Hz accurately - I would say, DC simulation would show probably more accurate result for this very low frequency.

In your simulation we could see that the 'signal' was also visible a few layers lower. Could it be that the current you used (10A?) was more than the skin depth of the refence plane?
- that is what I would expect to be different. But it is only my guessing.
znp2015 , 07-22-2021, 07:31 AM
@qdrives maximum length of 2 cm. there is no termination used for I2C for 400 kHz. In the scope, I have not seen resonance on signals.

@robertferanec that is the problem. The system has different frequency speed values. So considering one frequency speed of the whole system may not have the results we see in the real world.
qdrives , 07-23-2021, 01:08 PM
@znp2015
1) Is your question related to an analog signal or digital. Signal Integrity is mostly mentioned for digital signal, but you mention ADC_INPUT.
2) Keep analog signal away from digital.
3) Current flows in loops (schematic), but traces couple into whatever has provides the lowest impedance. If this is a plane in the return path, then the problems (EMC, crosstalk, etc.) will be lower, then when it is not.

The various videos to watch:
Do you separate Digital GND and Analogue GND, or not? What do you think is better?Links:- Rick Hartley: https://www.linkedin.com/in/rick-hartley-8571216/- Do...

The best animation to explain crosstalk I have ever seen! Thank you Eric.Links:- Eric Bogatin: https://www.linkedin.com/in/eric-bogatin-368860/--------------...

The best crosstalk explanation I have ever seen. What do you think? Thank you Eric Bogatin. PS: Please share, not because I would like to get views, but I be...

Do you pour copper on your signal layers or not? Thank you very much Rick Hartley. Credits to Daniel Beeker, Lee Ritchy and Susy WebbLinks and Credits:- Rick...

Do you know what I changed to improve the signals in the picture? What do you think?------------------------------------------------------Would you like to s...

What space do you use between tracks on your PCB?------------------------------------------------------Would you like to support me? It's simple:- Sign up fo...