Cross Talk and address/data bus
williajl , 05-09-2021, 10:59 AM
Hello,
I am in the process of wrapping up a board layout with standard peripheral bus composed of the standard address, data and control signal (WE,OE). I have a board stack up such that the reference plane is 0.1mm below the traces. The rise time from the processor is a 1.5ns minimum. When reviewing the cross talk calculations from various websites I end up with an insane value for any track above 10mm. The values are well over the V low for the chip set of 0.15*Vdd ~0.495V with a track separation of 1H (0.1mm) and maximum trace length for the bus of around 70mm. The only way I can get a reasonable number is to use a separation of 4H. In the past, I have always routed my address/data bus with separation of twice the trace width and never had any issues. I started watching several videos from Eric, Rick and Robert about victim traces and aggressor traces. This got me to rethinking my address and data busses. However, when looking at layout strategies, the track separations become unrealistic for anything I have seen or done. So, this got me to thinking. Is cross-talk only and edge event, I.E. only occurs at the rise and fall edges as the signal propagates down the track? I did a lot of searching and there seems to be no discussion on this. Therefore, I will pose this question here.
Is cross-talk only an edge event or is it a steady state coupling problem? The reason I ask is that traditional data busses will send their address signals first, and then some time later raise the control signal line, either WE or OE. Then at some time later, read the data at the receiver. If cross-talk is an edge event and not steady state, then this would make sense with the track spacing that I have used and what I have seen on other systems. If cross-talk is steady state, then it seems to me that the bus would never work with the traditional track separations I have used or seen.
Does anyone have further insight into this. I would really like to stay with my twice track width separation or actually just H if H >= 0.1mm for a given stack up for all of my parallel interface busses that I use on microcontroller designs.
Another thing that crossed my mind is what would happen if I created a split between adjacent tracks on the reference plane. In principal, this could break the coupling fields since there would be no reference between the tracks area on the reference plane.
Thanks,
James
I am in the process of wrapping up a board layout with standard peripheral bus composed of the standard address, data and control signal (WE,OE). I have a board stack up such that the reference plane is 0.1mm below the traces. The rise time from the processor is a 1.5ns minimum. When reviewing the cross talk calculations from various websites I end up with an insane value for any track above 10mm. The values are well over the V low for the chip set of 0.15*Vdd ~0.495V with a track separation of 1H (0.1mm) and maximum trace length for the bus of around 70mm. The only way I can get a reasonable number is to use a separation of 4H. In the past, I have always routed my address/data bus with separation of twice the trace width and never had any issues. I started watching several videos from Eric, Rick and Robert about victim traces and aggressor traces. This got me to rethinking my address and data busses. However, when looking at layout strategies, the track separations become unrealistic for anything I have seen or done. So, this got me to thinking. Is cross-talk only and edge event, I.E. only occurs at the rise and fall edges as the signal propagates down the track? I did a lot of searching and there seems to be no discussion on this. Therefore, I will pose this question here.
Is cross-talk only an edge event or is it a steady state coupling problem? The reason I ask is that traditional data busses will send their address signals first, and then some time later raise the control signal line, either WE or OE. Then at some time later, read the data at the receiver. If cross-talk is an edge event and not steady state, then this would make sense with the track spacing that I have used and what I have seen on other systems. If cross-talk is steady state, then it seems to me that the bus would never work with the traditional track separations I have used or seen.
Does anyone have further insight into this. I would really like to stay with my twice track width separation or actually just H if H >= 0.1mm for a given stack up for all of my parallel interface busses that I use on microcontroller designs.
Another thing that crossed my mind is what would happen if I created a split between adjacent tracks on the reference plane. In principal, this could break the coupling fields since there would be no reference between the tracks area on the reference plane.
Thanks,
James
qdrives , 05-13-2021, 09:43 AM
Yes, cross talk is an edge thing.
"...create a split..." - a split the reference plane? Bad idea.
70mm, with 1.5ns rise time, this seems more a termination issue.
Some video links (new to old):
"...create a split..." - a split the reference plane? Bad idea.
70mm, with 1.5ns rise time, this seems more a termination issue.
Some video links (new to old):
robertferanec , 05-15-2021, 03:01 AM
You are right. Simply to say, for example you may be able to route data signals from the same group closer to each other and separate strobe signals with bigger gap. What I imagine (and maybe would be interesting to simulate), there may be some crosstalk between data signals, however until the strobe arrives, it will all settle down. This is one of the reasons why I like to route together the tracks which belong to each other (I can route them closer) and then make bigger gap for other group of signals or strobe or clock signals. I do not like route tracks randomly with different tracks between them as then the edges may travel through different signals in different times and it may randomly and ocasionally cause problems which are super hard to find out, replicate or fix.
PS: Also, I have on my TODO list a video, which would explain difference between crosstalk calculated by an equation and a crosswalk in a real circuit. From what I have seen, it looks like the crosstalk in a real circuit will be lower then the crosstalk calculated from a simple equation (or online calculators).
PS: Also, I have on my TODO list a video, which would explain difference between crosstalk calculated by an equation and a crosswalk in a real circuit. From what I have seen, it looks like the crosstalk in a real circuit will be lower then the crosstalk calculated from a simple equation (or online calculators).
anovickis , 08-15-2021, 10:52 PM
Depends on the rate of your clock for the bus and length of the bus - it's primarily looks like an "edge" effect, that is once the lines are static things do settle down. The question then becomes are they settled down by the time clock pulse arrives.
It's more common to run into crosstalk when you have non-digital signals (ie without discrete thresholds), or if you have serdes generated digital which is constantly streaming.
.
Since this is a short run sticking to 2 times the trace width in separation distance should be ok
It's more common to run into crosstalk when you have non-digital signals (ie without discrete thresholds), or if you have serdes generated digital which is constantly streaming.
.
Since this is a short run sticking to 2 times the trace width in separation distance should be ok
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