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ibocakir06 , 10-27-2020, 07:28 AM

If someone wants to design a SoM and want to comply to the standarts Smarc or Qseven or Com Express, is there any comparison table or smt else to specify which is the best form factor?

Where to start when designing a SoM ?

I want to talk about with you about this topic.

The other question is if someone wants to design a SoM based Xilinx ZYNQ-7000 Family, where to route the PL(Logic) signals. In the spesification of 3 form factors I mentioned above, the signals or lanes or peripherals are already dedicated.

Thank you.
robertferanec , 10-29-2020, 06:15 AM
Form format: depends where you would like to sell. However it is often also about the space which you need for your chips (size of the board where you can fit all your components) and peripherals you would like to route to the connector (some formats do not have some interfaces). Often you would like to use the smallest size where your circuit will fit. If you are asking which format sells the best ... I do not know.

I am not exactly sure what you mean by the other question, but if you already have some software with some pins assigned, that would be the pin feature what I would use (so you do not risk, that moving the features will not work or will not be possible)
ibocakir06 , 10-31-2020, 03:19 PM
Actually you are right, the question i a bit different. There is no one true form factor. But I want to know, how can I decide which one we have to prefer.

SMARC Download ofSpecifications & Documents In order to download standard-related documents, you need to fill in your email address and accept our Terms of Use along with our IPR Policy. Smart Mobility ARChitecture (SMARC) // SDT.01The SMARC® ("Smart Mobility ARChitecture") is a versatile small form factor computer Module definition

If you check out this link, the SMARC spesifications are given and the pinout is dedicated. You have to route the interfaces with the dedicated pins.
robertferanec , 11-06-2020, 02:29 AM
I explained how we do it:

1) we select the one which supports our selected CPU architecture (e.g. you can see even the SMARC says: optimized for ARM and x86 architecture processors; may also be used with low power, tablet oriented X86 and RISC devices),

2) then we decide on the smallest size where we can fit all the chips we need to have on the module

3) and then we decide on specific type based on the peripherals we have (so we can take out as many pins as possible).
ibocakir06 , 05-14-2021, 03:54 PM
Hi again, I did not want to add a new topic.

I want to go ahead with SMARC however the specification says that the module PCB thickness should be 1.2mm to fit MXM3 connectors. I think this is really nonsense.

If I want to design the board 16 layer or higher or lower etc, how can I do the stack-up with 1.2mm thickness? I see several boards in the market with Intel processors or Xilinx SoCs or IMX8 series SoCs. Are they all really 1.2mm thick?
robertferanec , 05-17-2021, 04:04 AM
I have not used MXM3, but when I was designing for SODIMM, we had to use 1mm PCB and we were limited up to 10 layers.

Very basic calculation, if you have each layer 0.1mm, then for 1.2mm you could have max 12 layers. We do use some 0.075 layers, but I do not think you can have whole PCB like that (that would be 1.2/0.075 = 16 layers)
ibocakir06 , 05-17-2021, 04:20 AM
Hi Robert, thank you for your response,

I have attached a 10 layer stack-up from JEDEC DDR4 SODIMM reference guide. There are also 8 layers and 6 layers example stack-ups.

I suppose I understood the issue. We have to fit into 1.2mm thickness, so we can not go above 12 layers. The laminates are getting thinner and PCB construction is getting harder. There is nothing to do.

However when I google for "SMARC example stack-up" or "SMARC PCB stack-up", I have found nothing. I have sent an e-mail to SGET but they did not respond

Thank you.
Paul van Avesaath , 05-26-2021, 03:35 PM
i have desing a couple of boards wit smarc on them, never the smarc board but the thickness is defenitly not more than1.2mm.. bigger just simply doesn not fit inside the mating conncetor..
you can have more layers in there but pcb price will go up very heavy. and for large production numbers this is ok,but for a one off it will be very expensive and you have to talk with manufacturer specificly on this to see what is possible.

PCB stackups are pretty specific these days.. you have to think do i relaly need 10 layers or not.. what can is use in other ways like blind / buried via's and uVia's to gain enough options to get it done with less layers..
ibocakir06 , 05-27-2021, 01:40 PM
Thank you for you answer @Paul van Avesaath , OK, we must use 1.2mm thickness. The thing I can not understand is there are Intel processor-based SoM products on market which are SMARC compatible.

Example: https://www.adlinktech.com/en/Computer_on_Modules_SMARC

Are these boards all 10 layers or below?
Paul van Avesaath , 05-27-2021, 02:29 PM
yeah i can believe that,,, you really do need that many layers to do the HW. most if all the stuff is being supplied to the the connecter..that is the beauty of a SOM board. and besides that for IMX 8 is a 486 pin BGA so you do not need that many layers to do the fanout..most of those are power and gnd anyway.. if you are planning on having a go at it.. just try it.. i usually start by doing some fanout tests. placing a memory nearby and have a go at it.. the thing with SOM's there is not that much on there.,, it mostly is connected straight from the main CPU to the connector edge..

with the intel celerons its a FCBGA1090 that is a bit more of a challenge, but i have made designs with the Xilinx FG900 packages on 10 layers.. so i think i could squeeze out a few more on a 10 layers. most of these devices have the IO on the outside which does not need fan out to the deepest points of the BGA.

the BGA pitch is a harder item.. because you will run into via issues on the internal bal grid ranges.. but those can be mitigated with uVia stackups.. have a look at HDI designs this could give some insight in what you can achieve with a low amount of layers.. granted Signal integrity is something to whatch out for! but with todays simulation SW you can find out if there are any real issues before you go to prototype..

i think you can go up in layer count if your really need to but the cost will be very high.. and the material becomes more expensive too.. you will not get away with standard FR4.. (but if you do these designs.. please select something better anyway )

hope this helps.. don't be scared of giving it a go! even if it is just for fun.. just know that initial plans never survive first encouter with the enemy.. so dont give up on it until you are happy.. to be honest.. it think that i have designed a piece of bga layout almost 6 or 7 times before is was happy with it! (just for reference)
ibocakir06 , 05-27-2021, 02:41 PM
Thank you again for the answer,

Increasing the layer count is also increasing the cost OK, but converting TH via stack-up to an HDI stack-up is also increasing the cost

We experienced ITEQ180, FR408HR, or Megtron6 laminates. You are right, to decrease the trace width to fit 50 Ohm SE or 100 Ohm DP, choosing the right laminate is also critical. You are also right about the fanout issue. FFG900 fanout can be made with a 10 layer stack-up or 4/6 signal layers stack-up.

Happy works
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