yeah i can believe that,,, you really do need that many layers to do the HW. most if all the stuff is being supplied to the the connecter..that is the beauty of a SOM board. and besides that for IMX 8 is a 486 pin BGA so you do not need that many layers to do the fanout..most of those are power and gnd anyway.. if you are planning on having a go at it.. just try it.. i usually start by doing some fanout tests. placing a memory nearby and have a go at it.. the thing with SOM's there is not that much on there.,, it mostly is connected straight from the main CPU to the connector edge..
with the intel celerons its a FCBGA1090 that is a bit more of a challenge, but i have made designs with the Xilinx FG900 packages on 10 layers.. so i think i could squeeze out a few more on a 10 layers. most of these devices have the IO on the outside which does not need fan out to the deepest points of the BGA.
the BGA pitch is a harder item.. because you will run into via issues on the internal bal grid ranges.. but those can be mitigated with uVia stackups.. have a look at HDI designs this could give some insight in what you can achieve with a low amount of layers.. granted Signal integrity is something to whatch out for! but with todays simulation SW you can find out if there are any real issues before you go to prototype..
i think you can go up in layer count if your really need to but the cost will be very high.. and the material becomes more expensive too.. you will not get away with standard FR4.. (but if you do these designs.. please select something better anyway
hope this helps.. don't be scared of giving it a go! even if it is just for fun.. just know that initial plans never survive first encouter with the enemy.. so dont give up on it until you are happy.. to be honest.. it think that i have designed a piece of bga layout almost 6 or 7 times before is was happy with it! (just for reference)