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Redesign of a problematic pcb

ypkdani , 11-15-2019, 01:48 AM

i have follow the advanced hardware design and now i have redesign this pcb attached where we have had many problem related to:
⦁ Emi emissions in the points of the images
⦁ We have heating problem connected to the power absorbed by our device, 24W more or less distributed on the 5,7,12V.
⦁ Clock signal problem on the line MCLK to the codec audio U1
so in this relayout i have:
⦁ redesign the RMII ethernet net, metched the length, set a width as described in this guide pag.17, redesign the differential ETH nets TX and RX, remove the GND plane under the magnetic chip
⦁ Used the layer in different way. The TOP and BOTTOM layer are for high speed nets, layer 2 and 5 as GND, layer 3 and 4 for power supply and signals. In layer 5 a small part is used to renforce the 12,7,5V connection to the connector J3.
⦁ The SAI (or I2C) signal are designed using the width same as for the ETH RMII to reach the 50ohm impedence. A low length matching is done on these signal because i have more or less 5cm of signal length to the microprocessor that is on a different board. The MCLK work at 12Mhz

this is my first work with fast net, what are you impression about this layout? Do you have suggestion how to improve this?

Thanks all
robertferanec , 11-18-2019, 03:20 AM
@ypkdani that is like a lot to cover to answer. Please, do not expect that someone will answer all these your questions.

I had a look at placement around U4 power supply and I would not do it that way. I would not place the chip on one side and inductor on the other and + added additional tracks on other layers. That is quite critical connection and if not done properly can cause a lot of troubles (I would just place the inductor on the same side as the chip as close as possible). Here is some info from design guide:

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