DDR3L rules and constrains confirmations
Mihai , 05-16-2019, 02:22 AM
Hi,
This is just to confirm that I understand correctly the design guides for DDR3. I am designing a project which will use a 256x16 DDR3 chip with the 16-bit DQ bus configuration. I have read a lot of design guides even from both the controller vendor and the memory vendor. Since my configuration is point-to-point one, with a controller and one DDR3 chip, I have set the following design rules:
1- All the DQ, DM and DQS need to be length matched together, which include the following signals: DQ [0:15], LDM, UDM, UDQS, UDQS#, LDQS and LDQS#;
2- All the ADDR/CMD/CLK signal need to be length matched together, which include the following signals: ADR [0:14], BA[0:2],CLK,CLK#,CLKE, WE#,CAS#,RAS#,CS#,ODT and RST;
Please let me know if the rules which I have applied are correct, or if I missed something.
Cheers,
Mihai
This is just to confirm that I understand correctly the design guides for DDR3. I am designing a project which will use a 256x16 DDR3 chip with the 16-bit DQ bus configuration. I have read a lot of design guides even from both the controller vendor and the memory vendor. Since my configuration is point-to-point one, with a controller and one DDR3 chip, I have set the following design rules:
1- All the DQ, DM and DQS need to be length matched together, which include the following signals: DQ [0:15], LDM, UDM, UDQS, UDQS#, LDQS and LDQS#;
2- All the ADDR/CMD/CLK signal need to be length matched together, which include the following signals: ADR [0:14], BA[0:2],CLK,CLK#,CLKE, WE#,CAS#,RAS#,CS#,ODT and RST;
Please let me know if the rules which I have applied are correct, or if I missed something.
Cheers,
Mihai
Paul van Avesaath , 05-17-2019, 07:43 AM
Yes you are correct!
Mihai , 05-17-2019, 07:58 AM
Hi Paul,
Thank you!
Also, just to clarify something, even if its a 16-bit interface, the data maching has to be done within a byte lane, and not on the whole 16-bit data as described by me at 1. Right?
Cheers,
Mihai
Thank you!
Also, just to clarify something, even if its a 16-bit interface, the data maching has to be done within a byte lane, and not on the whole 16-bit data as described by me at 1. Right?
Cheers,
Mihai
Paul van Avesaath , 05-17-2019, 08:57 AM
You stated in your question that you would match all 16 dq and dqs pairs and dm so I would go with 16 and match those. Or change controller type to go to 8x then you are safe by doing dq0.. 7 dqs and dm of that set togehtor.. I am not sure what happens in the controller if you would route it with 8x and use it as 16x.. Normally the dqs and dm would manage read and write of the bytegroup so as long as it is matched it should work.. Again not 100% sure about it.. Maybe robert can tell..
Mihai , 05-17-2019, 01:26 PM
Hi @Paul van Avesaath, that's what I though too, when using 16-bit interface. However, I haven't seen it explicit said in any design guide which I read. All design guides says only about the byte lane, not both. Maybe @robertferanec can clarify this.
Cheers,
Mihai
Cheers,
Mihai
Paul van Avesaath , 05-17-2019, 02:24 PM
I think it should be fine.. But if Robert or anyone else can confirm you should be good to go!
robertferanec , 05-20-2019, 02:02 AM
@Mihai, some time ago we created a nice picture, maybe it will help you (T branch length matching picture attached below).
For data, you length match the signals withing groups - and the groups are created based on STROBE (DQS) signals. To make the answer short - usually you have 8 bits + Mask + Strobe ... so these are the signals what you need to length match (there are other cases e.g. when you use 4 bit memories, but I do not want you to confuse you). Strobe signal is basically used to tell when to read / write corresponding bits which are related to the STROBE ... so if you have STROBE for 8 bits, then you length match 8 bits data bus + mask and strobe for them.
From length matching point of view, 16 bit memories are 2 banks in one package ... they are still like two 8 bit data banks with MASK and STROBE, ... so you still work with them as individual banks (from length matching point of view, they are independent 2 groups of signals which can be length matched independently)
ADDR/ CMD/ CTL length matching depends on topology you use.
Google for "imx6 design guide", it can help you: http://cache.freescale.com/files/32b...6DQ6SDLHDG.pdf
Here is the picture (this is specific for iMX6, for other processors it may be different):
For data, you length match the signals withing groups - and the groups are created based on STROBE (DQS) signals. To make the answer short - usually you have 8 bits + Mask + Strobe ... so these are the signals what you need to length match (there are other cases e.g. when you use 4 bit memories, but I do not want you to confuse you). Strobe signal is basically used to tell when to read / write corresponding bits which are related to the STROBE ... so if you have STROBE for 8 bits, then you length match 8 bits data bus + mask and strobe for them.
From length matching point of view, 16 bit memories are 2 banks in one package ... they are still like two 8 bit data banks with MASK and STROBE, ... so you still work with them as individual banks (from length matching point of view, they are independent 2 groups of signals which can be length matched independently)
ADDR/ CMD/ CTL length matching depends on topology you use.
Google for "imx6 design guide", it can help you: http://cache.freescale.com/files/32b...6DQ6SDLHDG.pdf
Here is the picture (this is specific for iMX6, for other processors it may be different):
Mihai , 05-20-2019, 02:26 AM
Hi Robert,
Many thanks for your clarification, now it is clear for me.
Cheers.
Mihai
Many thanks for your clarification, now it is clear for me.
Cheers.
Mihai
Mihai , 05-20-2019, 06:27 AM
I have started the routing, while now I am thinking for a better placement to keep the tracks smaller than 5 cm. What do you think about this kind of placement? This is just a basic routing, to have an idea how the tracks will be arranged. After I am decided with the placement, I will start with the routing and the length matching,
Cheers,
Mihai
Cheers,
Mihai
Paul van Avesaath , 05-20-2019, 04:38 PM
Try to keep all signals on the same layer. I think your dqs pair now has an extra transition that the others don't.. You may swap the dq0 - dq7 in any order you want to make that happen....
robertferanec , 05-21-2019, 12:23 AM
What do you think about this kind of placement? This is just a basic routing, to have an idea how the tracks will be arranged.
Mihai , 05-21-2019, 01:30 AM
Its hard to find a reference design, due to the fact that they dont have it (Xilinx), or at least I didnt find it, However, I know some custom commercial boards which have DDR3, and I have look on their placement in order to ensure a clean and easy routing.Thank you @robertferanec and @Paul van Avesaath.
Cheers,
Mihai
Cheers,
Mihai
Mihai , 05-21-2019, 08:33 AM
And preliminary this is how it looks, I may do some later improvements, but this is it.
Cheers,
Mihai
Cheers,
Mihai
Paul van Avesaath , 05-22-2019, 02:41 AM
That looks excellent..
i usually do the address and command lines first because they are not interchangable like the DQ's so keep that in mind.. also address and cmd lines are slower than the rest.. so can have more tolerances and are not that critical in choosing different layers to route on.. (but always try and do as much of these on a single layer just dont go overboard becasue if you can make it fit much better on two layers.. then do that instead of introducing a lot of length ..)
i usually do the address and command lines first because they are not interchangable like the DQ's so keep that in mind.. also address and cmd lines are slower than the rest.. so can have more tolerances and are not that critical in choosing different layers to route on.. (but always try and do as much of these on a single layer just dont go overboard becasue if you can make it fit much better on two layers.. then do that instead of introducing a lot of length ..)
Mihai , 05-22-2019, 02:55 AM
Hi @Paul van Avesaath,
You are right, the address and commands should go first as right now I am routing them and also I had to make some adjustments in one of the data bank to have more space, however in my FPGA I can swap also the address and command lines. Also, the FPGA vendor has a tool for memory interface were I can put the final pinouts to validate the design, and if something is wrong with the pinouts this tool should tell me, but just to be sure I check them also manually.
Cheers,
Mihai
You are right, the address and commands should go first as right now I am routing them and also I had to make some adjustments in one of the data bank to have more space, however in my FPGA I can swap also the address and command lines. Also, the FPGA vendor has a tool for memory interface were I can put the final pinouts to validate the design, and if something is wrong with the pinouts this tool should tell me, but just to be sure I check them also manually.
Cheers,
Mihai
Paul van Avesaath , 05-22-2019, 02:59 AM
Are you sure about the address lines being swappable? Because if you are using a xilinx SoC I can pretty much say that the ddr43 interface of the processor is fixed.. Of is on Pl logic it might be different, but ps logic blocks were fixed (at least on the xcvu13p and on the zynq7045) maybe that changed however.. Good luck in any case!
Mihai , 05-22-2019, 03:33 AM
Yes, but I forgot to mention, they are swappable within a byte group of the FPGA I/O bank, have a look on a screenshot from UG586 document. I am using a Artix-7 FPGA
robertferanec , 05-22-2019, 04:26 AM
@Mihai, I would like to add, do not forget, routing 95% of BGA is simple, but last few pins can be extremely hard or impossible to connect. Be sure, you will be able to fan out the pins in the area where you route the memory signals - otherwise you may end up in situation when you will need to delete or re-do a lot of already finished layout. Have a look at our routing video, maybe it can give you and idea where to start: https://www.fedevel.com/welldoneblog...routing-video/
Mihai , 05-22-2019, 04:29 AM
Hi @robertferanec,
Indeed, the last few pins are extremely hard, you'll have to move existing tracks, vias etc to make space for them.
Thanks,
Mihai
Indeed, the last few pins are extremely hard, you'll have to move existing tracks, vias etc to make space for them.
Thanks,
Mihai
Mihai , 05-24-2019, 01:58 AM
Hi @robertferanec,
In your project OpenRex I see that you have routed the DDR3 interface, on both inner signal layers and the bottom layer with the same track width (~0.12 mm). This was the value which was required to route the tracks in order to have 50 ohm impedance for SE signals? Because in my case with 8 Layer stack-up (with 2 inner signal layers) the PCB company computed that I have to route with 0.16 mm tracks on inner layers and with 0. 35 mm on bottom layer. Or you have a custom stack-up with different dielectric thickness etc.?
Cheers,
Mihai
In your project OpenRex I see that you have routed the DDR3 interface, on both inner signal layers and the bottom layer with the same track width (~0.12 mm). This was the value which was required to route the tracks in order to have 50 ohm impedance for SE signals? Because in my case with 8 Layer stack-up (with 2 inner signal layers) the PCB company computed that I have to route with 0.16 mm tracks on inner layers and with 0. 35 mm on bottom layer. Or you have a custom stack-up with different dielectric thickness etc.?
Cheers,
Mihai
robertferanec , 05-27-2019, 10:32 AM
on both inner signal layers and the bottom layer with the same track width (~0.12 mm).
Stackup is attached
Mihai , 05-27-2019, 11:34 AM
Thanks Robert,
So there are to keep the 50 ohm impedance for DDR3 on that specific layer right?
So there are to keep the 50 ohm impedance for DDR3 on that specific layer right?
robertferanec , 05-28-2019, 01:27 AM
Yes, that is correct.
PS: In the stackup document you can see the required track width for specific impedance on specific signal layer.
PS: In the stackup document you can see the required track width for specific impedance on specific signal layer.
Mihai , 05-28-2019, 01:16 PM
Hi @robertferanec,
I see, on my 8 layer stack-up the PCB company calculated the track widths to the have controlled impedance (50 ohm SE) to be 0.16 mm on the inner layers and 0.35 mm on top an bottom layers, I have redone the DDR3 layout over 10 times, to find a nice placement and a good pinout with low skew. Even thought the layouts were correct, I decided to make it again, and as expected with more iterations the layout looks better. I will let you know when I have a layout which ok for me.
Cheers,
Mihai
I see, on my 8 layer stack-up the PCB company calculated the track widths to the have controlled impedance (50 ohm SE) to be 0.16 mm on the inner layers and 0.35 mm on top an bottom layers, I have redone the DDR3 layout over 10 times, to find a nice placement and a good pinout with low skew. Even thought the layouts were correct, I decided to make it again, and as expected with more iterations the layout looks better. I will let you know when I have a layout which ok for me.
Cheers,
Mihai
Mihai , 06-05-2019, 07:47 AM
Hi @robertferanec,
Following to improve the space usage on my DDR3 design I have found the following statement in vendor memory interface document (UG586_7series_MIS):
"For fly-by routing, address, command, control, and clock signals can be routed on different layers but each signal needs to be routed consistently in one layer across all DRAMs. Any signal layer switching via needs to have one ground via within a 50 mil perimeter range."
For me this means that I can route a specific signal from there on a dedicated inner layer, and other signal on other inner layer, am I correct? Or they refer to that all the signals need to be routed in the same way?
Cheers,
Mihai
Following to improve the space usage on my DDR3 design I have found the following statement in vendor memory interface document (UG586_7series_MIS):
"For fly-by routing, address, command, control, and clock signals can be routed on different layers but each signal needs to be routed consistently in one layer across all DRAMs. Any signal layer switching via needs to have one ground via within a 50 mil perimeter range."
For me this means that I can route a specific signal from there on a dedicated inner layer, and other signal on other inner layer, am I correct? Or they refer to that all the signals need to be routed in the same way?
Cheers,
Mihai
robertferanec , 06-09-2019, 02:27 AM
In theory, you always can route the signals any way you want - you just need to know what you are doing.
However, in reality, you may want to consider number of factors - for example, once you route signals from same group on different layers, you may be going into risk, that if you manufacture your PCB in different PCB manufacturers, you may get different results (I have seen this on some boards, because of I do not know ... a little bit different materials, or thickens, etc, ... do not forget, PCB manufacturer sometimes adjust stackup to meet impedance and if they change stackup thicknes or materials it can influence velocity and length of the signals - if you route all the signals same way, they will be influenced equally, but if you do not route them same way, they may be influenced differently).
We sometimes route signals on different layers, you just need to be careful - have a look for example at JEDEC DDR3 memory module reference layouts, that can help you to get an idea how they do it (the reference layouts are free you just may need to register): https://www.jedec.org/
However, in reality, you may want to consider number of factors - for example, once you route signals from same group on different layers, you may be going into risk, that if you manufacture your PCB in different PCB manufacturers, you may get different results (I have seen this on some boards, because of I do not know ... a little bit different materials, or thickens, etc, ... do not forget, PCB manufacturer sometimes adjust stackup to meet impedance and if they change stackup thicknes or materials it can influence velocity and length of the signals - if you route all the signals same way, they will be influenced equally, but if you do not route them same way, they may be influenced differently).
We sometimes route signals on different layers, you just need to be careful - have a look for example at JEDEC DDR3 memory module reference layouts, that can help you to get an idea how they do it (the reference layouts are free you just may need to register): https://www.jedec.org/
Mihai , 06-12-2019, 09:39 AM
Hi Robert,
Many thanks for providing me useful informations.
I have seen that the reset signal is not usually included in the lenght maching of the addr/ctrl/cmd group, however I seen that you are routing it toghether to have a close lenght, but with high clearance. We do not want to have some weird issues to do crosstalk. Should a 0.25-0.3 mm clearance be ok? I have done some calculations with Saturn and looks ok.
I my design with a 800 MHz controller and 1666 MHz DDR3, I have established a clearance of 0.25 mm between each signals. I think this should cover all the clearance rules. I have included also the packagge delays of the controller in the lenght maching.
Cheers,
Mihai
Many thanks for providing me useful informations.
I have seen that the reset signal is not usually included in the lenght maching of the addr/ctrl/cmd group, however I seen that you are routing it toghether to have a close lenght, but with high clearance. We do not want to have some weird issues to do crosstalk. Should a 0.25-0.3 mm clearance be ok? I have done some calculations with Saturn and looks ok.
I my design with a 800 MHz controller and 1666 MHz DDR3, I have established a clearance of 0.25 mm between each signals. I think this should cover all the clearance rules. I have included also the packagge delays of the controller in the lenght maching.
Cheers,
Mihai
robertferanec , 06-14-2019, 09:26 AM
When you calculate crosstalk, there are more important parameters, not just clearance. Have a look here, it can help you: https://www.fedevel.com/welldoneblog...s-as-possible/
Mihai , 08-09-2019, 03:18 AM
Hi @robertferanec et al,
After about a 2 mouth pause I started to work again on this design. Please have a look the attached images, regarding the rooting and length matching for the ADDR and BANK0 signal. Is good practice to do it like this, I have respected all the rules DDR3 design?
PS: it my first DDR3 design, the next one will be better.
Cheers,
Mihai
After about a 2 mouth pause I started to work again on this design. Please have a look the attached images, regarding the rooting and length matching for the ADDR and BANK0 signal. Is good practice to do it like this, I have respected all the rules DDR3 design?
PS: it my first DDR3 design, the next one will be better.
Cheers,
Mihai
Paul van Avesaath , 08-09-2019, 06:36 AM
nice work!, but looking at it I do get te feeling you could rotate your ddr chip 90 degrees , this way your overal length will be shorter.. but I do not know if you have to board space to do this.
also routing the length of one of your signal beneath the FPGA / uP is not a wise thing to do unless you do not have any other option.. this wil really restrict your rouitng options on that layer..
also routing the length of one of your signal beneath the FPGA / uP is not a wise thing to do unless you do not have any other option.. this wil really restrict your rouitng options on that layer..
Mihai , 08-09-2019, 06:43 AM
Hi @Paul van Avesaath,
thanks for your input. Indeed, I am aware that increasing the length under the FPGA is not wise, as I may need that space for other signals, But I am trying different layout versions to see which is the best layout.
I will give it a try with the chip rotated to 90 degrees.
Cheers,
Mihai
thanks for your input. Indeed, I am aware that increasing the length under the FPGA is not wise, as I may need that space for other signals, But I am trying different layout versions to see which is the best layout.
I will give it a try with the chip rotated to 90 degrees.
Cheers,
Mihai
Paul van Avesaath , 08-09-2019, 06:54 AM
no layout survives first contact 
at least for me it doesn't
at least for me it doesn'tUse our interactive Discord forum to reply or ask new questions.