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besim321123 , 03-16-2019, 10:54 AM

Now as you know STM present their product(STM32MP1) which can run Linux. So I plan to design SOM which is included STM32MP1 then baseboard for SOM. I downloaded all documents of STM32MP1 but I have some kind of problem. I decided to ask these question and I would like to get advice from you for this project.

As I said you , STM published all document which are datasheet, Altium document etc. I have examined these document and I saw that ST made the board 4 layer and length matching is not good for some addres. Tollerance has to be at least 25 mil right ? Maybe there's something that I don't know. Also I can not see anything about DDR routing guide in datasheet. So I was suprised. I think it has to be at least 6 layer. if I make it 4 layer. may it be problem ? I wanted to ask your idea. I am not sure how many layer should I use.

What are your recommendations about this project to successfully complete? what should I pay attention?

Your advices are important for me!!

Thanks!

besim321123 , 03-19-2019, 06:25 AM

i am wondering why anybody dont help me

mairomaster , 03-20-2019, 02:55 AM

Routed length includes the tracks to the termination resistors. You need to setup xSignals between the processor and ram pads, so you can get a proper measurement of the signal length.

robertferanec , 03-21-2019, 06:45 AM

@mairomaster is right. You can not be looking at PCB Panel -> Nets -> Routed length (this will show you the total routed length - you need to see only the length between the chips). You need to be looking into PCB Panel -> xSignals and you need to create xSignals so you can see only the length between chips (you can use also xSignal Wizard). Maybe this video can help: https://www.fedevel.com/welldoneblog...useful-things/

besim321123 , 03-21-2019, 06:59 AM

Thanks for your answers! What do you think about layer ? What are the disadvantages of making 4 layer? How many layer should i do ? What are your recommendations ?

robertferanec , 03-21-2019, 07:20 AM

I have not seen the reference board from STM - I am not sure how they do the reference planes. From the picture it looks like only 1 memory chip is connected to the CPU, it may be possible to use 4 layers - if pinout of the CPU is correct.