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Gabriel Mergh , 08-11-2025, 12:55 PM

Hello Guys!

I hope everything is okay!

I'm developing a PCB in Altium (version 20.2.4), and during the design process, I used the rule checking tools and didn't find any violations indicating a short circuit.

However, when I received the finished board, I detected a short between VCC (V_BAT) and GND. Interestingly, in the design, all the nets were correctly assigned, including the polygons I created in the four stackup layers, which were defined with the GND net. I didn't find any incorrect connections or in the elements.

Even after carefully reviewing the design in Altium and using the Design Rule Checker, I didn't find anything suspicious. This leaves me wondering if I made a mistake using polygons or if I overlooked a clearance setting.

I've been watching videos on YouTube @Robert Feranec and am considering taking a course to deepen my knowledge, but I would really appreciate your help in understanding what might have caused this short.

If you could guide me on any points I should review more closely or if you have any suggestions on what to look out for in these cases, it would be greatly appreciated.

Thank you in advance for your attention, and any help will be greatly appreciated!

Gabriel Mergh , 08-11-2025, 01:07 PM

I also suspect I made a polygon for cutout. These were magnetic field sensors, and reading their datasheets indicated that current could not be passed underneath them for better performance.

Neur0nZ3r0 , 08-12-2025, 12:48 AM

No idea how I'd be able to find your GND short like this buddy

Neur0nZ3r0 , 08-12-2025, 12:48 AM

Post schematics etc

Robert Feranec , 08-12-2025, 05:27 AM

If you can't find it in layout, it could be in PCB. I would take the bare pcb and keep cutting the VBAT until I would find the position where is the short circuit. In some of the comments I have seen someone showing a short circuit on a plane layer and Altium was saying everything was ok. Also, I have seen PCB manufactured with short circuit.

QDrives , 08-12-2025, 11:31 AM

You are using an older verion of Altium. If I recall correctly, if you had shelved polygons, they would not repour. You DRC also does not check them. However, when you export to Gerber, they are exported, which may cause the problem.
Secondly, like @Robert Feranec mentions, it may be a production fault. is it on one board or multiple? What is the resistance?
One way you may be able to get rid of it is by 'burning' it out. If it is a hairline, then just applying a low voltage high current to them the thin copper sliver will burn up.
Are your clearances big enough? Perhaps a via is off slightly causing the short. Or a layer mis-registration.
Highlight the net in question and check everywhere it is close to Gnd (in 3D as well!).

Gabriel Mergh , 08-12-2025, 02:06 PM

I'll try removing the polygons I applied to the top and bottom layers by burning and also remove the decoupling capacitors to see if that could be the problem. The boards that arrived without soldered components didn't have short circuits. Thanks for the tips, and I'll get back to you soon. If you have any other ideas that could help me understand the error, I'm open to hearing and understanding.

QDrives , 08-12-2025, 02:09 PM

I have had ceramic capacitors that were shorted.
With a bit of luck, the problematic component heats up the most.

Gabriel Mergh , 08-12-2025, 08:52 PM

Hello, I came back here after finding where the short circuit was on the board. I identified that it was in one of the magnetic field sensors, only after removing the sensor did the short circuit stop. My question now is whether using a polygon for cutout could have been the problem, since in the schematic I did as indicated in the datasheet.

I applied the polygon for cutout to all four layers:
- Top layer (signal)
- L2 (GND) - This one didn't have the polygon for cutout marked, as shown in the figure.
- L3 (I used it as power)
- Bottom layer (signal)

Although the datasheet doesn't ask for this, I had read that for magnetic field sensors, it would be ideal. But that might have been the cause of the problem. Does that make any sense?

QDrives , 08-12-2025, 09:52 PM

You have "polygon pours" and "polygon pour cutouts". But what do you mean with "*polygon for cutout*"?

As for the short circuit, the footprint with the (polygon pour) cutout shows a large thermal.
1) I cannot think of a reason to place a cutout when there is a thermal pad.
2) Probably too much solder on the thermal pad and that cause the short.
Do you have a part number of the component?

Pad 1 of the decoupling cap nest the sensor does not have a thermal relief.

Gabriel Mergh , 08-13-2025, 01:23 PM

Yes, the component is MLX90394 . And when i say polygon pour cutout, i mean what is in the image.
When i say thermal relief, do ypu mean the pad have to be change for thermal realief in the rule?

QDrives , 08-13-2025, 02:10 PM

Can you point where in the datasheet or application note it mentions opening the copper?
Thermal relief is (mostly) in the rules. TH and SMD pads have them, vias do not (advanced option).

Gabriel Mergh , 08-13-2025, 04:13 PM

The datasheet doesn't mention applying a cutout for the copper layer. I had applied it because articles I read said that for better functioning of magnetic field sensors it was recommended to do so. However, for this very reason I believe this was my mistake, and because I applied this poor cutout, it short-circuited after being soldered, compromising the entire board.

QDrives , 08-13-2025, 04:23 PM

No, the cutout should not be the cause for the sort circuit.
But I see the datasheet of Melexis is not very good.

Gabriel Mergh , 08-13-2025, 05:27 PM

Not at all, which makes the project very difficult.

Gabriel Mergh , 08-14-2025, 12:35 PM

Hello!

I'm here to update you on the other tests I did on the board. I want to share a problem I think might be happening to more people. We received more of these boards, and before we removed them, they weren't shorting out. When I removed the board with the detachable part, it didn't short out. So now I wonder if the problem was caused by removing the board "wrongly."This may have triggered the problem, as I have a VDD polygon that was very close to the end.

QDrives , 08-14-2025, 07:52 PM

Board outline clearance should be at least 0.3mm and for V-score at least 0.5mm.