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Question about DDR routing choice
Nick , 03-17-2025, 03:51 PM
Have a Dell motherboard here. Was looking at the layout and I noticed something interesting about the DDR traces. They do this weird interlocking thing. Why would they do this? Seems they are intentionally creating coupling between traces. My monkey brain can't figure out why..maybe one of you experts can educate me.
Robert Feranec , 03-18-2025, 03:32 PM
this can help you it is called tabbed routing https://community.cadence.com/cadence_blogs_8/b/pcb/posts/next-generation-hs-routing-with-tabbed-routing
QDrives , 03-18-2025, 08:16 PM
I see the subject of a new video with Yuriy Shlepnev.
Robert Feranec , 03-19-2025, 06:18 AM
he mentioned this on our last call
Nick , 03-20-2025, 09:42 PM
mind blowing. Thank you Robert. I was scratching my head. No one at my lab here knew what that was. Ill have to dig deeper...
ElHeim , 03-21-2025, 01:30 AM
@Nick I'm confused. Some sources point to Intel introducing it in 2020 (and there's a patent!), but Cadence seems to have offered it since 2016?
Nick , 03-21-2025, 01:15 PM
I'm confused too. I work for a semiconductor company and our grey beards are just as confused
Sniper2 , 03-25-2025, 08:27 PM
interesting
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