FEDEVEL
Platform forum

, 01-16-2025, 08:30 AM

I am working on a project with quite a few connectors going to several external components. I decided to be safe an isolate all of these connections each with optocouplers and isolated PSU (blue arrows).

Limitations / Restrictions:
- 4L stack-up due to budgetary constraints
- Form factor is set so I cannot change the shape of the board.
- Have to use these connectors.

This now brings up the question of the GND plane on L2. It seems frowned upon to have multiple GND sections as apposed to an "uninterrupted" GND plane. Referring to the image attached, I see no clear issue as long as I stick to routing over the appropriate GND sections only eg. All signals going to the uC should be routed over the 'system GND' pour on the L2 and not cross over a different GND or clearance area? I added some traces for reference running from the Optocoupler outputs to the uC. Both Optocoupler output and uC will have system ground as a return path.

I have added 0.5mm clearance between polygons with belonging to different NETS on L2.

QDrives , 01-16-2025, 05:04 PM

So what is your question?

, 01-17-2025, 05:14 AM

@QDrives - than k you for your response.

Whether dividing the layer into multiple different isolated GND sections is really an issue providing I only route corresponding signals on each GND section of course?

Ideally I would put all the connectors on one side or alongside the perimeter therefor simplifying the system GND plane, but unfortunately there is just not enough room to do so.

QDrives , 01-17-2025, 09:05 PM

Still not very clear to me but let me put things differently and you can confirm.
1) There is a requirement to galvanically isolate sections. Correct?
2) The Gnd layer (layer 2, below top) is split to create sections with isolated Gnd.
3) All signals travel over their reference Gnd. Only optocouplers and DC-DC converters are used to cross the splits. Do note that this is not always the case!
4) You have added a capacitor and high resistance (>= 500k ohm) resistor in parallel between the Gnds for high frequency noise and discharge of static build-up from occurring.

, 01-18-2025, 08:19 AM

Hi @QDrives

My apologies for not being clear enough.

1. This is correct. As these 'off-board items' will be connected using longer wires and might be placed in noisy AC environments (or exposed) I thought to best to isolate them rather than just protect them with eg. TVS diodes.

2. Yes indeed, GND is on layer two. I am trying to do all routing in L1. Might need to use L3 for **some** routing in more densely pack areas but it will not be in the isolated sections as these are easy enough to do on L1.

3. This is correct. No trace will either cross split area or different reference GND.

4. In was hoping not to do this in order to maintain galvanic isolation as I need to meet Intrinsic safety standards. My plan was to add a copper pour on L1 as well and stitch it to the GND on the second layer.

I will also be adding stitching vias around the periphery of the isolated GND sections.

Thank you for the assistance, it is much appreciated!

QDrives , 01-18-2025, 05:24 PM

1. What you write does not imply "required" nor do I think isolation helps here. Beter to apply differential signaling. You also still need protection eg. TVS diode.
3. No mention where it is not the case.
4. You still have even with the capacitor and resistor. Do note that EMC is also required for safety and these components are for EMC.

, 01-18-2025, 06:46 PM

1. Just for confirmation, I have placed TVS diodes on every "line" coming in from a device connecting to the PCB. I will rather be safe that having comebacks. I can also DNP these if we find no transient spikes when testing. Are you of the opinion that isolating these inputs by means of optocouplers are not needed?

3. hhmmmm... seems I have been taught wrong then in terms of galvanic isolation. I was under the impression that there will be some leakage current regardless and true galvanic isolation is therefor not achieved. I will place Class-Y capacitors, at least of the fail, they will fail 'open'. Will place them in parallel then with maybe 1MΩ resistors.

Thank you for your patience, it is much appreciated!

, 01-18-2025, 07:03 PM

I was indeed wrong about the isolation... also found this in an article by Cadence :

*"Y-type capacitors can meet galvanic isolation requirements that ensure safety, and it is their capacitance value that controls the emissions." *

Thank you for pointing that out!

QDrives , 01-18-2025, 07:38 PM

".*..if we find no transient spikes when testing.*" -- Depends.... Do you need to do EFT and surge tests on these connections due to cable length?

, 01-19-2025, 05:41 AM

Just for our my sake... not required by client. Just a habit I picked up as I have had too many incidents in the past where components connected to inputs (whether it was FETs or GPIO had random failures once clients got their hands on it 🙂

, 01-19-2025, 05:42 AM

I requested client for a full set of external hardware so I can try and duplicate an absolute worst case installation setup.