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Danie , 10-07-2025, 03:12 AM

I'm designing a PCB that requires two alternate connection points (which are on opposite sides of the board) for a UART RX signal, where both traces route to the same MCU RX pin. So from what I've researched, my understanding is that the unused connector becomes a stub. In my research on signal integrity and stub length, it talks about how edge rate is the point of concern, but I can't find anything about how much this impacts a UART signal. (UART baud rate is 115200 and the signaling standard is just TTL (not RS-232 or RS-485)

I'm very new to this topic, so I was planning on designing the board in a way that allows me to measure and validate the signal integrity myself. I want to know: what is the best practice for designing the PCB to diagnose signal integrity issues on a UART line caused by a stub?

The current testing strategy I was considering is the following, and I'm hoping someone can confirm whether or not this is valid or if there were other problems that I might be unaware of:

1. I am uncertain on where the test point locations should be for the oscilloscope. Should it just be one near the MCU's RX pin before the traces split to the connectors? I also don't know how the test point should be "placed" or designed so that I'm not creating ANOTHER stub.
2. I was planning on placing a 0 ohm resistor in series on each of the traces to the connectors. That way I could populate only one resistor for the first connection I'm testing to see the "stub-free" UART measurement, and then populate the second 0 ohm resistor to see how the UART signal has changed now to see the effect of the stub. Will this work or not in practice?
3. I'm not sure about what limitations exist on the oscilloscope or probes are that I should be aware of when I do this. I'm worried that maybe the oscilloscope or probes themselves will modify the signal in some way that I'm not aware of (because I'm still learning) and I'll think that it's the result of the stub itself, rather than the measurement limitation.

Thank you!

Robert Feranec , 10-07-2025, 07:21 AM

often if you have to split buses like this, you can consider to use buffers

Robert Feranec , 10-07-2025, 07:30 AM

personally I would not spend too much time by thinking about that. I would implement the simplest option (eg 0R resistors) and I would add support for an alternate option that will work in 100% cases (e.g. buffer, but not fitted by default). Later, in specific case I would just fit the simplest option, test it and if there would be problems I would use the alternative option.

Danie , 10-07-2025, 11:33 AM

Ok thank you very much! I will admit I spent too much time thinking about it... do you have any recommendations on the placement of the test point for it so that I don't introduce other problems, and also the consideration for the oscilloscope & probe? I'm still learning and trying to design it the safest way

Robert Feranec , 10-07-2025, 01:18 PM

I don't know how your board will be used, if it is only one specific situation or if it can be used in multiple different systems, but if it can be used in multiple systems measuring it by scope may not give relevant results. If you are worried, maybe you can try to simulate it, maybe this video can help: https://youtu.be/VBmuJfcMeFk

QDrives , 10-07-2025, 08:35 PM

For UART Rx you would need an AND gate to combine the signal from two inputs.
For Tx you would have a stub, or you use a buffer too.
With 115200b/s SI is not a problem. EMC might. For that you need to match the impedance more or reduce the signal rise time.