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HasanTheSyrian_ , 10-30-2025, 09:25 AM

here the yellow inner signals have a gnd pour under them, can i move the plane up closer to the signals and move the power vias down

HasanTheSyrian_ , 10-30-2025, 09:33 AM

also what about a small part of the signal trace going over no reference? other ground planes are far from the yellow signal trace, the blue pour is ground

QDrives , 10-30-2025, 08:43 PM

All signals will have a return current induced.
With up and down do you mean in the stack-up or the screenshot?

QDrives , 10-30-2025, 08:47 PM

Via's always have a impedance discontinuity.
The faster the signal rise time, the more important the via geometry becomes.
You would need 3D field solvers to optimize above a certain frequency.

HasanTheSyrian_ , 10-30-2025, 09:06 PM

i meant moving the ground polygon that cuts the power plane, i have moved the ground up close to the signals and created a pour for the power pins. you can see it here in the middle where the arrow is pointing

HasanTheSyrian_ , 10-30-2025, 09:06 PM

my concern now is that some power pins dont have a direct path to the 3v3 DC/DC converter

HasanTheSyrian_ , 10-30-2025, 09:07 PM

the power plane is cut, i put ground under the signals of the inner layers

HasanTheSyrian_ , 10-30-2025, 09:07 PM

https://www.altium.com/viewer/?token=9KTUhJSzQkmh5w8BTxysEbHp

HasanTheSyrian_ , 10-30-2025, 09:07 PM

you can see the design here

QDrives , 10-30-2025, 09:55 PM

The 'yellow' trace marked in yellow can be routed (mostly) on the top.
Place some capacitors to couple 3V3 to Gnd in the green circles and use the 3V3 as the reference for the other signals.
The capacitors are to couple the signal back to Gnd.
Then you can have the whole board with a 3V3 plane.
Move some vias to be within those green circles grouping them so you so not have to place so many capacitors.

HasanTheSyrian_ , 10-31-2025, 07:47 AM

so i just place capacitors connected to the 3v3 plane and ground next to the vias? what about the 1.8v signals?

QDrives , 11-02-2025, 01:14 AM

It is a 3.3V power polygon right? The capacitor is of the power polygon, not of the voltage of the signals.

HasanTheSyrian_ , 11-02-2025, 08:23 AM

if i remove the ground cut like you say it becomes a 3v3 plane, except for the sides which i moved back to decrease the chance of shorting with the ground planes

HasanTheSyrian_ , 11-02-2025, 08:23 AM

im asking about the 1.8v signals too, as far as i remember Bogatin saying that the power plane should be used as a refernce only if the signals have the same voltage

QDrives , 11-03-2025, 03:21 AM

No, not that I know of at least. But you do need capacitors as it is not the power rail that you want the return signal on, but Gnd.
Usually you have decoupling capacitors near your ICs, so you can use those too.

HasanTheSyrian_ , 11-03-2025, 10:34 AM

what about

HasanTheSyrian_ , 11-03-2025, 10:35 AM

making the power plane a ground plane and routing power on the signal layer

HasanTheSyrian_ , 11-03-2025, 10:55 AM

that way power and sig get a good reference

QDrives , 11-03-2025, 04:14 PM

That is (often) not a problem. I never use a power plane.