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KA , 01-14-2025, 06:02 AM

Hi All,

I am designing a 6-layer PCB using the JLCPCB controlled impedance stackup JLC06161H-3313 with a thickness of 1.0mm. The trace width and gap on these layers are 0.1mm each, vias with 0.2 mm hole and 0.4mm dia. Cost considerations are significant when moving from 6 to 8 layer board; a 6-layer board costs $35, whereas an 8-layer board is $91. Hence my choice for a 6 layer board.

The configuration is as follows:
- Layers 1 and 6 for signal routing, with components mounted on both sides of the board
- Layers 2 and 5 are ground planes
- Layers 3 and 4 for signal and power

The design includes a dense layout with an STM32 BGA package and routing for peripherals like I2C, SPI, UART, Ethernet, MicroSD, ADC, TIM, CAN, and USB. Controlled impedance is specifically applied to the SD, USB, and Ethernet traces.

I am concerned about potential crosstalk between Layers 3 and 4, which feature orthogonal routing without a ground plane between them. Could you advise on the suitability of this design or highlight any potential issues with this setup?

QDrives , 01-14-2025, 08:54 PM

This would only be a concern when you have either high speed or sensitive circuits (signals) running in parallel. Most traces seem to perpendicular.

Robert Feranec , 01-15-2025, 06:04 AM

you can try to play with different stackups, but there may be difference in price. for example this stackup could be interesting

Robert Feranec , 01-15-2025, 06:05 AM

Robert Feranec , 01-15-2025, 06:06 AM

for the stackup above you would have layers L3 and L4 far away from each other and you would have them close to their reference layers L2 (L5)