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DDR3 CLK Termination?

ATHONOR , 11-22-2023, 09:20 PM
Hi I am working on a project which based around a the SanCloud BeagleBone Enhanced (started before I was involved).

Looking at the SanCloud Design, they have used 2 x 8-bit DDR3 ICs in mirror configuration to achieve 16-bit 1GB RAM. From what I can gather, due to using two IC's they have included VTT termination to improve signal integrity.

Now for production, it is not ideal to put both DRAM IC's on either side of the board - and we are opting for the single-sided DRAM placement. I have noticed that the SanCloud does not terminate the DDR3 clock signals.

Reviewing the Artwork, I believe they have not terminated CLK signals because they have used T-branch routing for the clocks (Via'd up in the middle of the mirrored ICs, and then routed out from the via to both IC balls in a T, as CLK pin is in the middle row balls, hence a short distance) - See poorly attached drawing.

So my question is.. they haven't termianted CLK signals. I assume this is because the T-branch is effectively the same as point-to-point, and with such little distance can get away with it. However, for my design where two IC's will be some distance away - I will also need to include the termination for CLK signals?

https://github.com/SanCloudLtd/BeagleBoneEnhanced/blob/master/V1G/SanCloud_BeagleBone_Enhanced_1G.PDF (Schematic - DDR3 page 9)

https://www.ti.com/lit/ds/symlink/am3358.pdf (Texas Instruments CPU Datasheet - DDR3 Clock Termination page 181)

https://github.com/beagleboard/BeagleBoneEnhanced/blob/master/SanCloud_BeagleBone_Enhanced_1E_Final%20Artwork%20Prints.PDF (Artwork for SanCloud design)
Robert Feranec , 11-27-2023, 08:18 AM
for point to point it is clear, you terminate at the end of the track - so when signal arrives at the end of the track it doesnt reflect back. However, in T branch you will have more ends and connecting termination resistor on each end is not the solution as then they would be connected in parallel on the same signal. So in your case, if you only have one chip, you can add termination ... if not needed you can always leave it unfitted.
ATHONOR , 11-27-2023, 07:04 PM
I have two chips, so I think I need to terminate the clock as well.

Which the only reason I can see SanCloud haven't done that on their design is because of they have routed the CLK in Branch topology, and the rest of the DDR3 in fly-by-toplogy
Robert Feranec , 11-29-2023, 05:25 AM
so you have two chips, but only one fitted?
ATHONOR , 12-03-2023, 12:04 PM
I have two 8-bit DRAM ICs fitted on a single side of the PCB. The SanCloud example uses mirror placement.

The San Cloud terminates all typical DDR signals except the clock. I am trying to understand why they have not chosen to terminate this signal.

My understanding is because SanCloud used T-branch routing for the CLK signals only, the reflection is likely to be minimal due to small stub.
Robert Feranec , 12-04-2023, 06:42 AM
I don't know why they didn't use it. do the memory chips you are using have termination on the clock signals?
ATHONOR , 12-06-2023, 09:30 PM
No not for the CLK lines, on DSQx yes (MPN: AS4C512M8D3LC-12BIN https://www.alliancememory.com/wp-content/uploads/pdf/ddr3/AllianceMemory_4G_DDR3L_AS4C512M8D3LC_June2020_Rev1.0.pdf)

It's not a massive issue as I will include it as per another TI reference deisgn, just wanted to understand why it was omitted. Thanks anyway Robert 😆
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