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Xsignals Wizard for DDR3 Clock with serial resistor

baoNG , 12-17-2018, 09:46 PM
Hi Sir.
I'm routing 2 DDR3 using T-branch and X-signals in AD16.
in net DRAM_CLK i'm using 2 serial resistor from SOC to DDR3.
but when i run Xsignals Winzard it can't detect net DRAM_CLK like image.
How do to fix it.
mairomaster , 12-18-2018, 05:40 AM
From the schematics screenshot it's not clear if you have differential pair directives for DRAM_CLK0_P/N (similarly to DRAM_RCLK0P/N). That might not be related to the issue but it's a problem by itself.
baoNG, 12-18-2018, 06:58 AM
Thankyou for answer, i defined differential pair directives for DRAM_CLK0_P/N in another sheet. Probably not the problem there
robertferanec , 12-18-2018, 05:52 AM
You can create the missing xSignals manually. Design -> xSignals -> Create xSignals
baoNG , 12-18-2018, 06:55 AM
Thankyou Sir, i have another question, why SOC from China is very cheap. for example: allwinner H3 1.2Ghz or Rockchip RK3329 just 5 usd, and TI AM335x 800Mhz is 20 usd. i wondering to choose chip for my project.
Paul van Avesaath , 12-19-2018, 12:52 AM
sometimes it has to do with supply and demand. also sometimes it's about how many they already made.. maybe quality has a big factor in this.. other capabilities.. stabilities... testing capabilities.... MTBF....long delivery time... .. for a high end application I would not go with the allwinner because maybe you cant get i t anymore within a years time.. TI usually provides long livity. so you can get that exact same chip / die for the next 10 years for instance.. so to conclude.. is it for a one of project that you will make once and only at this time then go with the all winner.. if it is something you are planning to manufacturer for the next 2 or more years.. you have to look at the supply chain for every component to make sure you do not have to redesign in the future..
hope this helps.
robertferanec , 12-21-2018, 12:50 AM
If you are planning to design a serious product, you may want to use a reliable chip manufacturer. If you go for a manufacturer from china, you are not only risking, that your chip will not be available in a few years, most chip manufacturers from china have very poor support (poor documentation, design guides, reference designs, software, etc. - this can cause you a lot of headaches and delay in development).
baoNG , 12-21-2018, 08:50 PM
Yes, thankyou so much, and return to routing problem, i using 2 DDR3 t-branch, and i describe like image.

example: in group ADDR_CTRL, i using net A0 and A1 to represent group ADDR_CTRL.

(rule 1)> A0 to DDR3_1 will be matching with A1 to DDR3_1, and A0 to DDR3_2 matching with A1 to DDR3_2.

(rule 2)> A0 to DDR3_1 need matching with A0 to DDR3_2, it is necesssary? if it needed, how to setting this rule in Altium, because in Altium i just can setting (rule 1)

robertferanec , 12-25-2018, 08:25 AM
there are usually more rules in T-branch design, but basically, this is the concept:
1) you need to be sure, that signal will arrive at the same time from CPU to all the memory chips (this is needed to be sure that your memory is going to work ok)
2) you need to be sure, that all the branches have same or similar length (this is needed to keep signal quality high)

Some time ago I created a video which could help you: https://www.fedevel.com/welldoneblog...useful-things/
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