jpartis1 , 07-19-2018, 08:06 AM
Thank you for that reply, it helps clear some things up in my mind.
Unfortunately, the OCT on the Cyclone IV E doesn't seem to support 3.3V LVTTL, which is what is required for the SDRAM (IS42S16320F-6TLI).
That would been a wonderful option to have, but after searching through many documents, I was disappointed OCT isn't supported in my configuration (I could be wrong).
I do know that the pin drive strength can be adjusted though, and that may help with matching.
I spoke with I very nice representative over at ISSI, and they informed me that 50-60ohm was a popular recommendation from many controller's vendors (including Altera) with SDRAM.
He went on further to say that the drive strength of the SDRAM is typically in the range of 30ohm, which is stronger than the 50-60ohm impedance of the transmission line, and can cause signal reflections, therefore, they recommend ~20ohm serial termination on the transmitter.
The issue is, on the bi-directional data lines, both the FPGA & SDRAM will be driving at different times.
How do you position the series terminators in this case?
ISSI recommends placing the resistors in the "middle", which makes sense.
do you agree with this?
On a side note, I found your 12 layer stackup and noticed that it contains uVias for only signal layer 1 & 2 to ground plane between them, but not to signal layer 3, and same on bottom.
I was wondering how you use the uVias in your routing.
Can you please explain how your architect your layers, ie, what goes on what layer?
Do you use uVias to make ground connections, to internal plane, or do you use through hole vias for this?
Would you please elaborate on these so that I can get a clear understanding, and so that I will be better able to select the proper uVias, stackup layers, etc.