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baoNG , 03-25-2018, 07:38 AM

Hi Sir,

In this PCB-Stackup. Can I layout Higspeed Signal (DDR3) in layer 4?
L3 and L4 look like similarity of the conditions.
Thanks you very much.

robertferanec , 04-02-2018, 10:10 AM

If L2 and L5 are solid GND, yes, you can. Just double check what would be track width for 40-50OHMs (depends what you need) and if you will be able to keep enough space between tracks to minimize crosstalk. I mentioned this, because for this kind of stackup the 50OHM track width may be quite wide (you can see from the table, 0.15mm for 55OHMs) and with wide tracks it may not be easy to route the interface if your board will be very small.

baoNG , 04-02-2018, 10:44 AM

Thanks Sir for answer!
Yes. I'm routing BGA with pitch is 0.65mm and DDR3, 0.15mm for 55ohm is difficult.
How to fix this stackup for tracks smaller than before?

robertferanec , 04-02-2018, 03:01 PM

To make tracks thinner, you need to bring the reference layer closer to signal layer. Have a look at our other stackups: https://www.fedevel.com/welldoneblog...your-projects/

baoNG , 04-02-2018, 08:06 PM

Hi sir!
i just have a question. i have Pcb-project of Olinuxino, in this pcb, all tracks in all layers is 5mils and space is 5mils, Diff100 or Diff90 or SE is 5mil.
why it still work?

robertferanec , 04-03-2018, 11:10 AM

Depends on many factors (e.g. speed, distance / size, etc ... ). Sometimes even not properly done layout will work ok (some rules are sometimes too strict and can be broken) ... or sometimes the boards work ok - most of the time, they just occasionally freeze or crash.

baoNG , 04-03-2018, 12:07 PM

Yes. I see. Thanks you very much, this is the first time i'm routing high speed pcb, i hope everything is fine.