FEDEVEL
Platform forum

prabhu , 02-02-2018, 01:00 AM

Hello Everyone,

I am prabhu new to this forum
Right now i have almost finished my Schematics which is containg FPGA,MicroProcessor,HDMI, SDI Serializer, etc which is big board which is containiçgn mulitple connectors

My Questions are?

1) I am thinking of doing Fanout FPGA/ followed by DDR3 routing with proper length matching without configuring layer stack up whether it is good idea to begin like that or it is advisable to define the layer stack up first and then do the FANOUT and length matched Routing of the DDR3

please help me with some guidelines of your experience so that it could be helpful for me to do my first high speed design board
Any help ideas or ideas would be greatly appreciated and it could be really helpful for me in my future projects

Have a nice day

Thank you
prabhu

mohsin_qau , 02-02-2018, 01:08 AM

In my opinion, it is better to build up your stack first. Because this is two sided job. You have to consult first your selected PCB Fabricator. He will provide you complete capability list. On the basis of this info, you will build stack up. Then ypu have to apply Altium rules for Length macthing and other high speed as mentioned in Fedevel Acadmey.

prabhu , 02-02-2018, 01:52 AM

Hello Thanks for your reply

Actually i am thinking of making the layer stack up by myself because there were some examples and guidelines for the layer stack up in the internet but i dont know how to configure layer stack up for both FLEX and RIGID PCB

mohsin_qau , 02-02-2018, 02:04 AM

Stack up will be build up by yourself. But the Core/Prepeg ratio, dieclectric constant and thickness will be with mutual concern. Because this is the base of impdence controlled routing. After this stack up , you will be able to fanout your FPGA.

robertferanec , 02-02-2018, 10:27 AM

To start layout, you do not need the exact stackup, but you may want to at least add the layers which you need. Also, we always route digital signal tracks wider (0.1mm), so we can make them thinner to match impedance when we receive the final stackup (e.g. by the end of layout we will make the 0.1mm tracks thinner to meet 50 OHM impedance for specific stackup, in final PCB thickness of these tracks is usually between 0.075 - 0.1mm). Also, keep anough space around differential pairs, once you have final stackup you may need to re-route them.

Here are some examples of stackups what we use, it may be helpful for you: https://www.fedevel.com/welldoneblog...your-projects/

prabhu , 02-05-2018, 01:28 AM

thank you so much for your kind reply robert

Actually my aim is to do the FPGA fanout first to in order make the connection in the future part of the pcb and then i wanted to Route the DDR3 high speed signal between FPGA and DDR3 without any Vias on the top layer so my guess is inorder to do this work i do not need the complete stack up right ? please correct me if am wrong in my guess

however in order to do the length matching between FPGA and DDR3 do i need complete stack up also?

These questions may be silly but honestly this is the first high speed multilayer board so inorder to do that i need to have some minimum guidance thats why i have posted my question here

Any ideas or suggestion would be greatly helpful for me

robertferanec , 02-06-2018, 10:24 AM

My previous answer should help you.

Initially you do not need the final stackup, but you may want to create the layers which you may need. Route the tracks wider and once you have the final stackup, adjust the track width to make them thinner to meet the impedance - that is how we do it.

prabhu , 02-12-2018, 02:14 AM

Hello Robert

Thank you so much for your kind reply

as you have mentioned in the Advanced Layout course lesson 2
DDR3

All the address signals after fanout from the processor it is advised to do the layout all the address signals in the same layer or i have do the layout some of the address signals in the bottom layer and some of the address signals in the middle layer and some of the address signals in the Top layer because of my placement i can not able to find the way the to do the layout on the same layer

will it cause any consequences if i do route in the address signals on the several layers please suggest me some ideas if possible

Thank you
prabhu

robertferanec , 02-12-2018, 07:49 PM

Very often, if you have symmetrical PCB stackup (so the inner layers have very similar properties), the signal may be routed also on different inner layers (be careful about length matching and consider length in VIAs).

However, if you are planning to route on top/bottom + inner layers, be aware, that there is difference in propagation delay (in speed how the signal travels on different layers.

So:
- the safest way to route is to use same layers,
- if you know what you are doing then you can use different inner layers,
- however, if you mix signals of same group between top/bottom and inner layers, then you really need to understand what you are doing. You need to do layout based on propagation delay and you may want to simulate the interface (I do not do this).

Of course, it may also depend how fast the interface is, but even for slower interfaces we never use the top/bottom + inner layer mixed groups.

PS: Doing layout is sometimes very hard

prabhu , 02-13-2018, 01:15 AM

HelLO Robert
thank you so much for your kind reply

i did the fanout for the ddr3 on Top layer and all ADDRESS signals on the middle layer 3 and all the data signals on the middle layer 4

I have a question in the Advanced layout IMEX6 processor for the DDR3 layout you have mentioned that it is the standard layout for all the DDR3

i have seen teh rules for the ddr3 that you have used 0.1mm track width and 0.1 mm clearance between the tracks

but my pcb fabricant has given me that 0;165 mm track width for the 50 ohm impdenance signle ended so i am stuck in between my layout i have designed based on the your tutorial suggestions but my pcb fabricant has given me other rules for the design

so can i aske my pcb fabricant to re analyze the stack up and impednace for the corresponding layer

culd you please suggest me some ideas this is the first time am doing layout for the DDR3 so i am bit confused please help me

Thank you

prabhu

robertferanec , 02-13-2018, 09:02 AM

Track width depends on stackup ... and PCB manufacturer ... and price of your PCB. Low cost PCB manufacturer will be suggesting wider tracks (0.15mm is standard low cost minimum track). So, if you are planning to use a cheap manufacturer, then you may be using different "starting default values" e.g. 0.2mm track width and 0.2mm minimum clearance (once you finish layout you may adjust the track width down to 0.165mm). However for more complex boards, it is not possible to use 0.2mm (the track would be too wide and it would not be possible to route some tracks, e.g. BGA chips) and we use 0.1mm track width and 0.1mm minimum clearance - the final 50OHM tracks are then: 0.1mm or thinner.

So, you have two options: make your tracks wider (if you can), or you need to adjust stackup. Here you can download examples of stackups what we use: https://www.fedevel.com/welldoneblog...your-projects/