USE DISCOUNT CODEEXPERT30TO SAVE $30 USD
Questions regarding DDR3 layout
matf33 , 03-10-2017, 01:43 PM
Currently I am working on a 6 layer PCB with a Sitara processor and one DDR3 memory chip. It is my first design with this type of memory and I have several questions.
My stackup from L1 to L6 is as follows: signal - GND - signal - signal - PWR - signal
The byte net classes are routed on separate layers (L3 and L4), but the address control bus is routed on both L3 and L4. Since of the core thickness of approx. 1mm, the signals routed on L4 are about 2mm longer than the ones routed on L3. I am able to compensate the length tolerance by making all L3 signals 2mm longer, so far so good.
As suggested in the datasheet (design rule excerpts are attached), I included termination resistors on the address control bus to VTT. The design rules related to the connection of these resistors cause me some severe nightmares. I am not able to match the resulting stub length AS = top routing from DDR3 memory ball to via + effective via length (see attached ddr3_term.png) within the demanded 25mils. Right now I decided to keep the routing length between the DDR3 ball pads and the via as short as possible and only match the overall net length.
On the reference designs (same layer stackup and same routing) TI neglects their own design rules and doesn't care about the imbalanced stubs. Like in my design, they only compensate the overall skew of the address control bus. What is your experience regarding stub length matching ? Is it a must, or a nice to have design rule ? I would be very grateful if any experienced developer could give me some advice. If it is not critical I would keep my current design.
I also have two further questions:
Does a maximum skew of 25mil within the DDR3 net classes mean, that the length limit of all signals in the net class is clock /strobe length +/- 25mil or is it required that the clock / strobe length is the longest ?
Does the reset line require length matching ? Since it is not listed in any class, I assume it is an asynchronous signal and does not require matching.
Thanks in advance for your help. I would also like to thank Robert for sharing his knowledge, this is a really great platform for engineers.
Best regards from Germany
Matthias
My stackup from L1 to L6 is as follows: signal - GND - signal - signal - PWR - signal
The byte net classes are routed on separate layers (L3 and L4), but the address control bus is routed on both L3 and L4. Since of the core thickness of approx. 1mm, the signals routed on L4 are about 2mm longer than the ones routed on L3. I am able to compensate the length tolerance by making all L3 signals 2mm longer, so far so good.
As suggested in the datasheet (design rule excerpts are attached), I included termination resistors on the address control bus to VTT. The design rules related to the connection of these resistors cause me some severe nightmares. I am not able to match the resulting stub length AS = top routing from DDR3 memory ball to via + effective via length (see attached ddr3_term.png) within the demanded 25mils. Right now I decided to keep the routing length between the DDR3 ball pads and the via as short as possible and only match the overall net length.
On the reference designs (same layer stackup and same routing) TI neglects their own design rules and doesn't care about the imbalanced stubs. Like in my design, they only compensate the overall skew of the address control bus. What is your experience regarding stub length matching ? Is it a must, or a nice to have design rule ? I would be very grateful if any experienced developer could give me some advice. If it is not critical I would keep my current design.
I also have two further questions:
Does a maximum skew of 25mil within the DDR3 net classes mean, that the length limit of all signals in the net class is clock /strobe length +/- 25mil or is it required that the clock / strobe length is the longest ?
Does the reset line require length matching ? Since it is not listed in any class, I assume it is an asynchronous signal and does not require matching.
Thanks in advance for your help. I would also like to thank Robert for sharing his knowledge, this is a really great platform for engineers.
Best regards from Germany
Matthias
robertferanec , 03-13-2017, 06:36 PM
Hi Matthias,
- I would say, the AS length matching requirement is maybe only for two memory design?
- I would not call AS stub, it is connection to the memory. I would call AT stub.
- From the table (#13) it looks to me, that ADDR/CTRL should be in tolerance of +/-50mils from CLK. But double check what CACLM means.
- We make RESET similar to ADDR/CTRL, but we do not length match it.
- I would say, the AS length matching requirement is maybe only for two memory design?
- I would not call AS stub, it is connection to the memory. I would call AT stub.
- From the table (#13) it looks to me, that ADDR/CTRL should be in tolerance of +/-50mils from CLK. But double check what CACLM means.
- We make RESET similar to ADDR/CTRL, but we do not length match it.
matf33 , 03-15-2017, 03:35 PM
Thanks for your response Robert. I finished the design now, not matching the length of the reset line and also not matching the stub length. CACLM is the longest distance of the address/control bus between processor and memory chip by the way. In the case of the AM335x routing of address line 8 is expected to require longest routing length.
Use our interactive Discord forum to reply or ask new questions.