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ep.aniketh@gmail.com , 01-23-2017, 01:10 PM

How many layers are recommended when making the processor board like Raspberry Pi or Beagle Bone Green Wireless? I do not have much insight into this right now. If I need to choose many layers down the line probably it would be too late. Could you please give me more insight based on your experience?

robertferanec , 01-24-2017, 12:07 PM

Have a look at reference boards or design files of the board. Also, this may help you: 3 STEPS How to determine / calculate number of PCB layers

Possibly, you can search on my welldone blog for "stackup": http://www.fedevel.com/welldoneblog/?s=stackup

I hope this helps

ep.aniketh@gmail.com , 01-25-2017, 04:56 PM

Hello Robert,

The link which you posted was very informative. Thank you for sharing that. I was going through the Hardware Design Guide for i.MX6 UL processor. I came across this page where in they say that the processor board can be done with 4 layers which is very strange. I have seen the evaluation kit of the same processor, where in the project manager says that their evaluation kit is made of 4 layer PCB. I have attached the screenshot for your reference. Could you please comment on this? We are a start up and we cannot afford if use many layers on the PCB.

robertferanec , 01-26-2017, 11:01 AM

You are not only one asking the same question about this UL processor I saw the design - I saw even the datasheets from which is not clear if the memory runs on 200MHz or 400MHz.

Did you find where they specify the stackup?

MadhuWesly , 05-18-2017, 05:39 AM

Hello Robert,

I am developing a Processor Board which is based on iMX6 Quad and features 2 GB RAM(4 - 4Gb DDR3L RAM chips), 8 GB eMMC. For this, I would like to use 6 Layer stack-up(Signal/GND/Signal/Signal/Power/Signal).

Can you please clarify the following doubts/uncertainties:
1. Will there be any problem if I go with 6 Layer PCB instead 8 layers or more?
2. Is the 6 layer stack-up(if it can be preferred) which I have provided above perfect?

I am going to use the above stack-up since I need minimum 4 layers to route DDR3 memory.

3. How to overcome the problems when there are two adjacent Signal layers(High-speed signals)?

Awaiting your reply...

mairomaster , 05-18-2017, 05:58 AM

1. I am not convinced if it's even possible to do such design with a 6 layer stackup. If you haven't done so, take a look at the REX board design form fedevel (Open REX as well). There is a good reason why they use more layers. It's not only very very difficult and time consuming to fit the design in a low layer number stack, but you also often need to do too many compromises which increase the risk. I don't have much information about you board but take a look at similar designs to get an idea of how many layers you need.

2. The six layer stack you provided seems good to me by itself.

3. Make sure you have a thick core in the middle of the stack, so you have a good separation between the consecutive signal layers.

MadhuWesly , 05-18-2017, 06:31 AM

Thanks for your reply. Actually, I already have gone through REX board and Sabre board. In Sabre board he uses 8-layers, But the thing is the number of signal layers is "4", which we can achieve through this 6 layer stack-up(Signal/GND/Signal/Signal/Power/Signal). That's why I am preferring to go with 6layers for cost optimization. Of course there are few advantages like EMC improvement and reducing interference if we go with 8 layers. Please suggest me the best way to design my board with 6 layers with better performance.

Awaiting your reply...

mairomaster , 05-18-2017, 06:39 AM

If you are sure you will have enough space for all the signals, what about the power? Probably you will need quite a few power rails. How would you do those by having only 1 power plane?

MadhuWesly , 05-18-2017, 07:02 AM

Many of the power rails are routed on top and bottom. And I want to use the power plane dedicatedly to 3.3V(or any other VCC which has more number of connections). Please suggest me the tips/Guidelines which are used to design my board with 6 layers with better performance.

Awaiting your reply...

mairomaster , 05-18-2017, 07:17 AM

It's a huge topic, I can't even recall particular tips which I can give you. How much experience do you have with similar designs?

robertferanec , 05-18-2017, 08:13 AM

I would not relay on top and bottom power planes. 1. do not forget on top and bottom layers you will have pins and VIAs and it may not be possible to create high quality power planes under CPU. 2. I am not sure if you could fit them all there

When we were designing OpenRex, we were looking into different stackup options. We tried to route OpenRex on 8 layers, but by the end of the design we had to add 2 more layers. Number of layers may also depend on size of your board, technology (through hole VIAS only or you can use uVIAs), etc.

Maybe have a look at the other iMX6 CPU .. UL or which one it was? They have reference design on a very simple PCB.

MadhuWesly , 05-22-2017, 06:26 AM

Hello Robert,

This is Madhuwesly.

Can you please go through the attachment(1 and 2 parts) which is 8 Layer stack-up and impedance control details which were taken from the PCB manufacturing company.

I am thinking that maintaining the 9.5 or 9 mils(For maintaining 50 Ohms) track width on the signal layer will be more difficult and requires large space while routing. Isn't it?

And PCB total board thickness also is high(2.11mm).

1. Can I ask them to recalculate the values in order to make the track width values small.?
2. Can you tell me the track width and spacing values you maintained for imx6 REX, just to know whether I can go with present values or I have to ask the manufacturer to recalculate?


Awaiting your reply...

robertferanec , 05-23-2017, 09:24 AM

These may help you:

• Download PCB Stackups – Free for your Projects
• 5 Steps to define a Custom PCB Stackup
• How to design PCB stackup

1. yes, you should talk to your PCB manufacturer to adjust your stackup
2. see the articles above, they may help you. All the stackups used in REX projects can be found in the Download section (you will need to register at http://www.imx6rex.com/)

MadhuWesly , 05-24-2017, 10:55 AM

robertferanec , 05-24-2017, 11:46 AM

What do you think?

I could write you the answer, but .. you know .. you should learn to do it by yourself So, have a carefull look at what they are suggesting and their notes and tell me if you can see something weird.

MadhuWesly , 05-24-2017, 10:07 PM

One thing I could find weird is "maintaining Drill- 0.15mm, and Pad- 0.5", will it create any difficulty in terms spacing? Actually, I didn't find anything weird other than that.

Please let me know if you find any issue if we go with the specifications.

robertferanec , 05-25-2017, 08:11 AM

Check out their note about minimum TW (track width) for inner layers, change the units to mils and compare it with what they are suggesting - especially L3 / L6 100OHMs

MadhuWesly , 05-27-2017, 02:14 AM

Hello Robert,

Thank you for your previous response.
I would like to get one more confirmation, please clarify this:

SoC specifications: iMX6Q - MCIMX6Q5EYM10AC of pitch 0.8mm, and Ball pad diameter - 0.5mm.
Manufacturer minimum specifications: Drill size - 0.15mm, Pad size - 0.5mm.

Can I achieve 0.1mm minimum spacing between Ball pad to Via(0.5mm-pad, 0.15mm-Drill) when I place vias in the BGA?

When I was going through your course you mentioned your design rules as: Min clearance: 0.15mm - sqpinternational, Drill size: 0.2, and diameter:0.45mm.
How would it possible to you to maintain 0.15mm spacing after placing 0.45mm Via in the BGA?

Awaiting your reply.

robertferanec , 05-28-2017, 09:46 AM

You can check our open source OpenRex project: http://www.imx6rex.com/open-rex/

You can download the Altium files and measure all the dimensions you need to know. I will help you to answer your questions.