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Power Plane

mostafa222 , 01-14-2017, 11:59 AM
Hi Dear Robert. How Do You Draw This Power Plane? Indeed, My Question is how You Can guest the shape? i see the open rex board. for example, you draw the shape in below figure. how do you decide what is the necessary shape? do you use the track to connect component to power plane or you draw the power plane in way that can cover that component?
robertferanec , 01-16-2017, 01:57 PM
When we do placement, we always think ahead and try to imagine how the power planes will look - then it is quite simple, just draw the plane under all the power pins and use VIAs to connect it. Initially we connect all the power pins by tracks (instead of drawing power plane, we draw tracks) and then based on the tracks we can see the required power plane shape. When we are improving/finishing the layout, we delete power tracks from the particular layer and draw the polygons instead.
mostafa222 , 01-16-2017, 09:12 PM
Thanks dear robert. I learn many things from you.
Avinashdara , 07-05-2017, 10:27 AM
Hi Robert, I am designing a 8 layer board with iMX6Q. For accommodating power planes, we want to split the power planes(we have two power planes in my stack-up). Could you suggest me the best possible way to create split power planes so that there will be less effect to signal integrity?
mairomaster , 07-06-2017, 01:41 AM
The simple rule is don't use the split plane layer as a reference for high-speed signals. In case you definitely need to, make sure the important signals don't cross split planes and stay over the same plane.
Avinashdara , 07-06-2017, 05:42 AM
Thanks for the reply @mairomaster. As you said, it's not preferable to use a split plane layer as a reference layer for high speed signals. I have to use the split power planes, as imx6Q BGA has VDDCORE, VDDSOC, etc. voltage rails that carry high current. So, could you please suggest a best way on how to mitigate the signal integrity issues that I face with split power planes.

I do have an second option for creating different voltage polygons on the top layer. But I am not sure of the problems I face with this.
robertferanec , 07-06-2017, 06:16 AM
I am not sure how easy/difficult it is to do the QUAD on 8 layers. I believe we wanted to make OpenRex on 6-8 layers, but we ended up with 10.
Avinashdara , 07-06-2017, 06:42 AM
Thanks for the reply @robertferanec , I know its little difficult to go with 8 layers on iMX6Q, we have only 8 layers option from the manufacturer's side. So, could you please suggest me the best way to create polygons or split power planes in a way that I can meet good signal integrity, less EMC issues.
robertferanec , 07-06-2017, 10:43 AM
One of the problems why we increased the number of layers to 10 were power planes.
Avinashdara , 07-06-2017, 11:26 PM
Thanks for the reply @robertferanec. May I know the Do's & Don'ts that I have to follow for creating polygons on signal layers
robertferanec , 07-07-2017, 07:04 AM
We sometimes create mix layers (tracks + polygons), no problems. We are just careful - we keep bigger clearance between the planes and signal (e.g. in case the plane is noise we need to be sure we are not routing close to it)
Avinashdara , 07-07-2017, 07:34 AM
Thanks @robertferanec What's the maximum and minimum clearance that I should maintain between planes and signal ?
robertferanec , 07-07-2017, 11:58 PM
Simple answer is - as much as you can. You probably would like to hear absolute numbers, but these depends on your stackup and the signals. Have a look at some of our designs to get some ideas - you can download the Altium files. Check distance and see the stackup: http://www.imx6rex.com/
Avinashdara , 07-08-2017, 07:09 AM
Thanks @robertferanec We will look at the design files and get some pointers
Avinashdara , 07-08-2017, 07:56 AM
Hi @robertferanec Unfortunately the free version of Altium is not available. We faced the same issue during the Fedevel course. Is there any possibility to view imx6Rex design files in any open source EDA tools like KiCAD?
robertferanec , 07-10-2017, 08:53 AM
You may try to import the Altium files into KiCAD, but I am not sure if that will work oki.

I think Altium has a viewer, maybe that could help? However, I do not know what are the capabilities of the viewer and what are the conditions to get one.
MadhuWesly , 07-26-2017, 10:43 AM
Hi Robert,
I have designed an HDI PCB, in that I have created multiple polygons in different layers for a single power net. For example, consider we have VDDSOC power net, for this I have created polygon on L1(Top layer), but the created polygon is not solid(it is like discontinuous islands) that is why I have again created polygon on L3 signal layer as well in order to make it strong plane.

Actually, I do not know if it is correct way or not. Will it create any problem?
Please let me know if there will be any serious problem with this approach in my board.

Thanks & regards,
robertferanec , 07-27-2017, 10:13 AM
I often make partial polygons on top/bottom layer and then more solid polygon also inside PCB. No problems.

PS: Also, for very high currents we draw exactly the same polygons on multiple layers.
MadhuWesly , 07-28-2017, 11:47 AM
Thanks for the reply Robert, thats a valuable information to me. Please let me get clarification on few more doubts:

1. In the following image the component is a PMIC which is generating supplies like 2A, 1.5A, 700mA, etc. I have drawn the traces in such a way that the trace width is small at the PMIC pins and increased trace width as it goes out. I also created polygons in different layers for the source.
a. Will it be able to carry the required current to the destination properly?
b. What is maximum acceptable length till that we can maintain small trace width and then make the trace wide?
c. please look into the components placement around the PMIC and give better suggestions.

2. Do we have to maintain good amount of spacing between control signals, enable signals and other signals like power traces, or any other noise signals?

awaiting your reply.

Thanks and regards,
mairomaster , 07-31-2017, 02:36 AM
Prioritise placing the big output inductors as close to the PMIC as possible. You can put most of the small capacitors on the bottom layer, so that you have more space for the inductors at the top. That will allow you to use thicker tracks for the outputs.

Cross-talk should be less of an issue in the case - just try to be sensible.
MadhuWesly, 07-31-2017, 04:59 AM
Can you please reply inlines to the questions.Thanks in advance.
robertferanec , 07-31-2017, 07:03 AM
@MadhuWesly, you may want to have a look at our Switching Power Supply course: https://www.fedevel.com/academy/onli...design-course/

Possibly, you can download our OpenRex Altium project and check out how we did the placement and routing of PMIC: http://www.imx6rex.com/open-rex/

a) you need to check maximum current for tracks and VIAs. Simple and free tool to do that is Saturn PCB toolkit: http://www.saturnpcb.com/pcb_toolkit.htm
b) c) for high currents and important loops in power supply I often use polygons instead of tracks. Usually the placement needs to be done the way, that current loops between inductors, transistors and output bulk capacitors are as small as possible. The best is to read layout section of a power supply chip e.g. have a look at this document (search for "PC Board Layout Guidelines"): https://www.intersil.com/content/dam...6/isl6236a.pdf

2) Read the document from 1 b) c) that may help you. You may need to be careful about routing signals close to some of the power supply signals (e.g. gate or tracks which are going to be very noisy)
MadhuWesly , 08-11-2017, 02:58 AM
thank you Robert.
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