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Quickest and easiest to fabricate fan-out for 0.5mm pitch BGA

Scribe , 11-24-2016, 01:10 AM
Hi guys,

I'm working on a 6-layer design involving a 223-pin BGA with 0.5mm pitch (ball size 0.3mm) with a 16-bit DDR3 controller involved. Currently routing a track between two balls is resulting in a track width of 0.1mm and a spacing of 0.077mm.

Now the real trick is, I need this design fabricating rapidly and as suitable for low-cost mass production as possible. Many of the prototyping houses I've approached have quoted 3-5 days for this PCB because of these constraints, one recommendation I've had is to increase spacing to 0.08mm and reduce track width to increase yield but I'm interested to know if anyone else has an opinion on the best way to fan-out this kind of BGA to make it as quick and easy to produce as possible?

Many thanks
mairomaster , 11-24-2016, 02:04 AM
3 - 5 days is super fast. For high-end boards with 10-14 layers normally it takes 15-25 days lead time.

I don't think you have many options. If you had more layers you could have routed the outer row on the top and the 2nd and 3rd rows on internal layers. That way you wouldn't need to route between pads. I am not sure if you can do that on 6 layers though. What type of vias are you using?

I've noticed manufacturers often rather prefer thin tracks, than less spacing.

What about your impedance? Do you have a particular stack already with particular track widths/gaps that you need to use? You can agree with your manufacturer on those parameters so it works both for you and for them at the same time.
robertferanec , 11-24-2016, 09:57 AM
I would reduce the track width for the second row under the BGA to be lower than 0.1 and fan it out. Once you are out of the BGA, put the track width to 0.1 (or change the track width to the width which is required to meet your impedance). Some PCB manufacturers are able to meet stricter rules in a small area in one place of PCB.

I would fanout the first row directly and the third row through VIAs. I guess, the balls in the middle are power + ground, so you may be able to place VIAs between the pads and use polygons.
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