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znp2015 , 08-22-2016, 02:19 PM

Dear All,
First of all, I am really glad to know the FEDEVEL ACADAMY who learns me more about the layout and open the doors to to do the layout correctly.
Before that for our projects, I tried to find 2 layers’ solution to make the PCB and I think, it will work correctly without any challenges. But after watching the FEDEVEL ACADAMY more than 3 times in a month, I found that I should change my mind about the layout and PCB. By the way, because I think that starting with the Giga hertz board is not really working for me and our company does not need those high technology solution, I used LPC1788 with two RAM options (K4S561632 or MT48LC4M32B2F5-6A),= and one NAND flash from samsung (K9F2G08U0C). As I seen the embedded artist OEM board (http://www.embeddedartists.com/produ...pc1788_oem.php) and valuable FEDEVEL ACADAMY’s training. I decided to use the BGA version of LPC and for the RAM I used TSOP and BGA packages. As I try to find the technical solution, the best stackup layer is 6 layer. So I choose this stackup:
L1,L2(ground), L3(signal), L4(signal), L5(Power plane +3.3V), L6,
due to my PCB manufacture, I choose the track width 0.1 mm, clearance space 0.15 mm, and hole size 0.2.

In despite of Robert’s advice about the different size of uVia, BarriedVia, and ThrVia, I choose all the VIAs as 0.2 mm due to my PCB manufacture limitation for prototype PCB.

By the way I find some challenges between my learning from FEDEVEL ACADAMY and my hard experiences. I did not have a time and I just did layout 6 times from beginning in the 3 weeks (unroute and route all layout from beginning!!! I attached the 4 layers’ layout screenshots. I have done the PHASE1 but not PHASE2 to see the feedback from the forum. I want to ask my questions, I hope I did not do wrong many more in this layout.

1) the address, control, and data bus (32 bit) pins are really spread in the LPC1788 BGA package. This really makes the design hard. Because as I saw in the DDR3 layout, everything was designed wisely and engineer have good options to layout each buses locally. By the way, I have seen the embedded artist board and it works really nice. So I decided to continue choosing the LPC1788 in BGA format. I have this questions that how the line matching is important in this situation? Can I do the layout just considering the same topology for the important bus? In some application notes, it is mentioned that it just need to keep the same bus in the given area, for example less than 6 inches. I have this question, when the distributions of important buses are really spread, it means that the line matching is not important with high margin (as I learning from Robert, the line matching is for arriving the signal at the same time)?

2) The frequency of LPC1788 is 120 MHz and the RAM is less than 100 MHz. How is about the cross talk and the high speed design mentioned in the FEDEVEL ACADAMY. Does it consider as high speed frequency circuit?

3) I have used one NAND flash and RAM along with each other. Many works said that there is no need to buffer the EMC bus. Because I just have one NAND flash. But as I learned from many documents, I used just the NAND flash signals with a buffer. In this way,
LPC1788 ----- SDRAM
----- BUFFER ----- FLASH.
Is this buffer necessary and can help much to reduce the jitter or noise?

4) Before starting the PHASE2 layout, do you have any ideas about my work? Does it work well or not?

5) Any purposed idea to improve the work is appreciate.

Finally, thank you very much that read this long text.

And Finally special thanks to Mr. Robert who opens the valuable doors to me.

Best Regards,
Mostafa

robertferanec , 08-23-2016, 08:30 AM

Thank you very much Mostafa

I am looking at your screenshots. Please, could you mark what chips are the SDRAM, BUFFER and the FLASH? I can guess, but it will help also other people who would like to discuss your board.

znp2015 , 08-23-2016, 08:55 AM

Thank you so much again.
Please find the attached file.

znp2015 , 08-23-2016, 09:13 AM

excuse me for the mistake in the picture. i wrote SDRAM instead of SDCARD. left down side of picture.

robertferanec , 08-24-2016, 05:59 PM

Do they use the buffer in the reference design? If you are not sure, follow schematic and layout of an existing and reliably running board - I would do that.

znp2015 , 08-24-2016, 06:17 PM

The existing board has an external bus and they are buffered. In this regards, i also buffer only the pins used in the flash!

znp2015 , 08-26-2016, 09:41 AM

I am really glad to find someone that can answer my obvious questions :

1) the address, control, and data bus (32 bit) pins are really spread in the LPC1788 BGA package. This really makes the design hard. Because as I saw in the DDR3 layout, everything was designed wisely and engineer have good options to layout each buses locally. By the way, I have seen the embedded artist board and it works really nice. So I decided to continue choosing the LPC1788 in BGA format. I have this questions that how the line matching is important in this situation? Can I do the layout just considering the same topology for the important bus? In some application notes, it is mentioned that it just need to keep the same bus in the given area, for example less than 6 inches. I have this question, when the distributions of important buses are really spread, it means that the line matching is not important with high margin (as I learning from Robert, the line matching is for arriving the signal at the same time)?

2) The frequency of LPC1788 is 120 MHz and the RAM is less than 100 MHz. How is about the cross talk and the high speed design mentioned in the FEDEVEL ACADAMY. Does it consider as high speed frequency circuit?

thank you so much.

Best Regards,
Mostafa

znp2015 , 08-27-2016, 09:22 AM

I did some length matching for control, address, clock, and data signals. I do not really know that it is okay or not. Please give me a comment on this length matching.

robertferanec , 08-28-2016, 07:30 AM

You are designing SDRAM which works differently comparing to DDR3, so requirements for routing are different. SDRAM / NAND is more like a standard parallel bus. So you need to be careful about crosstalk / reflections and strobe signals coming at the right time (not before the data). Length matching between LPC and SDRAM and length matching between LPC and NAND would not be so critical (I would just probably try to make the strobe signals a little bit longer then data signals). But because you are placing two different chips on one bus, more critical will be the way how you route the tracks and the way how you place the chips on the bus (because of possible stubs when you are communicating with one of the chips). The most important is probably to keep the bus short. If you are not sure if you placed the components correctly and if you would like to check reflection for different scenarios of communication , you can try to simulate it. We were speaking about something similar here: http://www.fedevel.com/designhelp/fo...ecommendations

I hope this helps.

MartinHonig , 09-18-2017, 08:55 AM

Hello Robert,

I have noticed, that znp2015 used a combined footprint for SRAM (BGA or SOP) for a RAM. I am facing similar dilemma.

I would like to create an "universal" PCB for SLC NAND Flash memory (8-bit paralel bus + control signals connected to Cortex-A processor) for TSSOP48 and BGA63 packages. My concern is that when there is going to be the BGA package used, it is going to have roughly 8mm stubs because of unused traces to TSSOP footprint. I checked the NAND driver header for frequency settings across various vendors and we are talking about 15-40MHz, just to set a ballpark regarding how much high-speed we are talking about.

Is it an issue, or this 8mm long stubs should bearable in this application?

I also have concerns in term of erradiated EMI.

robertferanec , 09-18-2017, 02:16 PM

@MartinHonig, I would simulate it.

15-40MHz doesn't look much, so the interface may just work, but you are right, even after simulation, it will not be clear how this may influence EMI. The important factor will be rising/failing speed of the signals.

I guess, board may work perfectly and pass EMC/EMI even with the stubs, but .. there is this but ... and what if ...

Maybe, what could also be a solution (maybe what I would do), is place 0R resistors on the bottom under the BGA. it looks like there may be some space for them. If you find out, that you do not need the 0R resistors there (e.g. you run EMC/EMI tests with BGA and 0R fitted), then just remove them in next revision.

robertferanec , 09-19-2017, 05:16 PM

that's what I would do
PS: Posielam pozdrav do Ciech

yasin.bahrami , 01-30-2018, 02:37 PM

Hello
Someone can tell me what applications NandFlash and SDRAM are in connection to LPC 1788

robertferanec , 01-31-2018, 10:12 AM

Please, could you clarify your question? I am not really sure what you mean.

robertferanec , 02-01-2018, 10:26 AM

I have never used LPC1788, but I guess they may for example need additional memories to process and store some data.