Platform forum

Double DDR3 Routing

PeterZ , 07-30-2016, 06:08 AM
Dear Forum,
i try to route two DDR Chips in Fly-by but i can´t route all Adress an Control lines in one layer (L3). In the OpenRex Board some lines route in layer 3 and some in layer 8, but mixed up not from 0 to 7 and 8 to 15. I thought its important to route all Adr/Control Signals on the same layer? I have a 6 layer Board.
Another question is, why should i place the decoupling caps on the Top (same side as DDR chip) if i can place the caps closer to the vias on the Bottom?
Thank you
robertferanec , 07-30-2016, 06:43 PM
Hi Peter,
- Routing the group by same topology (on same layers) is a really good rule for everyone, it always works ok. However, there are situations when you may want to break it. Once you feel confident in doing memory layouts, you can do it the same way as on OpenRex (they do it the same way also on some memory modules), this helps with fly-by topology and it will work perfectly.

- If you have place on the bottom, yes, you can place the decoupling capacitors there.
PeterZ , 08-22-2016, 08:55 AM
Dear Forum,
i have place my DDR3 Modules and route the adress and control signals (length match still missing). But is it better to route it on the same layer(brown) or is it better to route the signals from the layer 4(blue) furthermore on layer 4(blue). If i route the signals from layer 4 to the processor in layer 4 the way is shorter and the via count is fewer.
robertferanec , 08-24-2016, 05:52 PM
I would definitely keep the same number of VIAs in the group.
znp2015 , 08-27-2016, 09:18 AM
Dear PeterZ,
If you have two DDR3, why don't you put the one DDR3 on top and another one on the bottom? I think in this way you can do the fanout of DDR3 very nice and use T-branch to do the layout. It was described perfectly at the advance course of FEDEVEL academy by Mr. Robert.

Let's try.

Best Regards,
znp2015, 09-15-2016, 12:03 PM
Dear PeterZ,You should take the advanced course from fedevel academy site.Best,Mostafa
znp2015 , 08-27-2016, 12:30 PM
I commented that there is an exception that you can use T-branch for DDR3 (thanks to Mr. Robert in lesson 6, advance course) when you are using imx6 and i think that your cpu is also imx6!!!
PeterZ , 09-11-2016, 04:12 AM
Dear znp2015, i have only 2 DDR3 ICs. I think T-Branch is better for 4 ICs. The Processor is a AM3358 Sitara not a IMX6. I found no lesson 6 on youtube.
Dear Robert, if i keep the same number of vias i route some lines "completely" in L3 and some in L4. This way is more easily but is this ok? In your IMX6 design you go on the same layer to route the Addr/ctrl lines to the processor. If i route it on L3 and L4 it has the same ground reference in the middle and the same count of vias, i think that is a good choice.
Thanks PZ
robertferanec , 09-13-2016, 04:34 PM
if i keep the same number of vias i route some lines "completely" in L3 and some in L4. This way is more easily but is this ok?
I am not really sure what do you mean - keeping same number of VIAs, but routing it differently. Would you just place a VIA on track and the VIA would go basically nowhere?
Arash yahyapour , 09-24-2016, 01:14 PM
Hi dear Robert Thank you for your helping in your mail.
I have a question about length matched on DDR2.
In my design I used a lot of square wave track.and the speed is 2.5 ns. I worrying for inductive noise.
my design is different with your design, you did to length match manually. but I used auto length matched.
Brown track is differential CLK.
do you announce your opinion please?
thank you
robertferanec , 09-26-2016, 11:07 AM
@Arash yahyapour have a look at this post and watch the video - it may help: High Speed PCB Design Rules (Lesson 4 of Advanced PCB Layout)

Three things what I noticed:
- I would make the space between "waves" bigger
- I would not use 90Deg angles (even some people say it's not a big deal)
- I am not really sure what is topology of the layout ... e.g. do you use T-Branch balanced topology for Add/Cmd/Ctl signals? Have a look at some of my older videos: Altium Designer – DDR2 routing and layout video
Arash yahyapour, 09-27-2016, 12:27 AM
Hi dear, first , thank you for your replay Ok. I used T-Branch between two DDR2 chips and they are balanced exactly.But these balance is different between two data line.for example T-Branch balanced between two chips in D0 line and it is 461 mil. but T-Branch balanced between two chips in D1 lineand it is 870 mil. however, both of total length is matched with less than 10 mil different's.I think there is no problem in here because Z-in from my processor to the two chips is the same.please, kindly if I'm wrong, notify to me.thank you Mr.RobertArash
robertferanec , 09-27-2016, 07:39 AM
Ok ... so both chips are connected to the same data bus? What is the frequency of the memory?

PS: Maybe it would help if in the picture you highlight the groups individually (e.g. Bank0 data group, addr/cmd/ctl group, etc.)
Arash yahyapour, 09-27-2016, 09:18 AM
Hi Dear Robertyes, both of chips are connected to the same data bus. and the frequency is 400 MHz, 2.5 nsplease let me, I doing to modify my design compatible with your opinionOk after that I will share it for youthe best regardsArash
robertferanec , 10-01-2016, 07:14 AM
By same data bus, you mean for example, D0 is connected to both chips? If yes, hmm, once you done the layout, maybe try to simulate it. Balanced T-Branch still could work ok for 400MHz Data signals, but it may depend on termination.

If I need to place memory chips on the same bus, I place them on top of each other (one on TOP and one on BOTTOM side of PCB), so the branch on data signals is as short as possible. This keeps quality of the signal high.
Arash yahyapour, 10-05-2016, 01:07 AM
Hi Mr. Robert.could you more explain about this sentences :"If yes, hmm, once you done the layout" and "but it may depend on termination",I have two pins named CS. by these pins I will activate one chip and deactivate another chip and send 16 bit data to one chip,in this case I need complete of data on one chip because it will doing for image processing and it will be easy for processing programming.I you have any opinion for this (my hardware) please kindly to send me.the best regardsArash
robertferanec , 10-05-2016, 08:20 AM
... I have two pins named CS. by these pins I will activate one chip and deactivate another chip and send 16 bit data to one chip, ...
This is exactly what the problem could be. You only talk to one of the memory chip at the speed of 400MHz and there is a part of track (connected to the non-active chip) "hanging" around which can cause reflections and which can influence quality of the signal (make it worse). That is why I place chips on top of each other, so the part of the track which is "hanging around" is as short as possible.

PS: We were discussing similar situation (but FLASH + SDRAM on same data bus) with much slower speed here - you can see how splitting the data signal can influenece the signal quality: http://www.fedevel.com/designhelp/fo...ecommendations
Arash yahyapour , 10-27-2016, 10:42 AM
Hi my friend how are you?
I changed my design accordance with your recommendation. and I send screenshot of Address and data and command, Separately,
I don't length match yet,
could you see thier, and send me your recommendation please.??
I want use midlayer1 (under top) for ground and differential clock only. is it ok ?
thank you
the best regard
robertferanec , 10-27-2016, 11:10 AM
Which tracks are data and which are address? Also, for data, you can do bit swapping to make the layout even better (to be able to place VIA directly close to pad) - you can safely swap bits within byte (e.g. you can swap bits D0-D7), do not swap bits between bytes. Have a look at some DDR2 recommendations: Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces
Arash yahyapour, 10-27-2016, 11:21 AM
From left: 1-All. 2-Address. 3-Data for DDR_1 . 4-Data for DDR_2 . 5- Commands
Arash yahyapour , 10-27-2016, 12:34 PM
Dear Robert I didn't get. could you explain about "you can do bit swapping to make the layout" please?
robertferanec , 10-28-2016, 08:49 AM
Double check your datasheet, but normally for DDR2 you can do bit swapping within bit or also byte swapping to make layout easier and better. This means, that you normally can change bits like D1 <-> D3, or D9 <-> D12, but you can not swap D1 <-> D12. So, you can connect the memory on the TOP and then based on the pads on the TOP "remap" the bits on the BOTTOM memory, so you can have same Data pad e.g. D1 in same position on the TOP as is placed on the BOTTOM (they are basically on top of each other). Then you can use a VIA close to the pad to route the signal and stubs are minimal.
Arash yahyapour , 10-29-2016, 01:41 AM
Hi Dear Robert thank you for your recommendation about swapping pin.
I search in my all of datasheets and internet. I just found this phrase:
<< Optional: Pin-swap within a given byte lane to optimize the data bus routes further.
Caution: Do not swap individual data bits across different byte lanes>>
So I have two questions:
- is it possible for address bus or No, it is just for data bus?
- If i swap for example D0 pin by D3 pin in my pcb, dose it means my sending data for these pins should be change?

could you send me a reference datasheet that it has been description about swapping pin.in DDR memories?
thank you Mr. Robert
have nice time
Arash yahyapour, 10-29-2016, 12:15 PM
after swapping pin in DDR2 ,Can I use DMA controller of ARM in my project?
robertferanec , 10-31-2016, 08:32 AM
- Data bytes only. Address lines are used to initialize and access memory chip registers and if you swap them, it would make problems.
- If you swap D0 with D3, you do not need to do any changes with sending data .... when you write data 01011100, they will be read exactly same back 01011100 (it doesn't really mater that you swap bits).

I do not have any specific datasheet for DDR2 swapping, you will need to google it

Do you know why you only can swap between byte? It's because each byte has control signals (DM, DQS) and these signals are tight up to the 8 bits. So you can not swap bits between bytes, because the control signals will be always same - and if you for example "move" D1 (from Byte 0) to D9 and length match D1 according the Byte 1, D1 will not work properly, because it's DM and DQS signals are length match according to Byte 0.
mtswan, 07-01-2022, 09:09 AM
Hi Robert... i am in the middle of your Advanced Hardware Design Course. Thank you for teaching! Can you elaborate on the bit swapping topic in terms of how the data does not change when you read/write it? Thanks!-Mike
Arash yahyapour , 11-16-2016, 01:10 AM
Hello drear Robert how are you? thank you for your description. I did your description to my layout. could you see their please? is it OK? If you confirm I will make it.
can I simulation my design in Altium before make?
the best regards
robertferanec , 11-17-2016, 01:05 PM
I do not see the data optimization which I suggested. All the DATA VIAs are still in the middle under the memory chip. After bit swapping you can place the VIA close to the pins - after pin swapping you can place same DATA signal on top of each other to minimize stub. That's how I would do it.

I do not simulate in Altium. For memories, I would recommend Hyperlynx - they have DDR Wizard to make the simulation easier.
Arash yahyapour, 11-17-2016, 10:31 PM
Thank you my friend , about pin swapping I do not it's. because it wasn't significant changes in my layout.but I carefully watched your training clip. you used 4 chip DDR memories and I used 2 chip DDR memories.this part of your layout (two memories, one chip on the top and another on the bottom) is exactly same as my layout. ( I mean vias under the chips). and your suggest me :separate data bus between two chips(D0 - D7 for chip of top) and (D8 - D15 for chip of bottom)<< I did it's.second, doing pin swapping: I thought a lot.I didn't it's, because it wasn't significant changes. and I should select on way of two way:1- I doing swapping pin, my PCB will be beautiful, and my programming flowchart will be complex and Hard.2- I do not swapping pin, my PCB will not be beautiful, and my programming flowchart will be simple and easy.and I select second way.is the matching length in by layout Ok? you kindly to me if answer me and suggest to mehave a nice timeArash
Arash yahyapour , 11-21-2016, 12:09 PM
Dear Robert! Do you answer me please?
Did I upset you?
robertferanec , 11-24-2016, 09:23 AM
@Arash yahyapour, I apologize for late replay, I was travelling.

It's very hard to review layouts, that is why I do not do it. I only can explain how I would do it and that is what I tried to do in my previous posts. So honestly, I am not really sure what I should answer. Do you have any specific question, what I can answer?
Arash yahyapour, 11-25-2016, 11:04 PM
Ooh,excuse me my friend, I understanding you. Yes I know, I want use just your experience. and this is your kindly that you sharing your experience in here. I design a single board computer for the first time. so I am worrying that, it does not run, after make. because this cost is high.I wish the best for youdovidenia Arash
robertferanec , 11-27-2016, 03:22 PM
@Arash yahyapour. I share my experience all the time, that is not a problem.

What you are asking for is review your layout and I do not do it. It's not because of you - it's because I don't do it. I receive number of similar requests every week (people send me their projects and ask me to review their schematic and PCB) and I say everyone no.

It is not possible - especially in cases if they do it different way as I would do it (it's your case). Then it is very hard to say what I think about it. Your case is even more difficult, as I have only seen pictures - that is very difficult for making opinions and telling if something is done ok or not. I am sure you understand.
Arash yahyapour , 12-17-2016, 05:34 AM
Hi dear Robert Thank you for your recommends, my PCB design is finish, I trying to import this PCB from altium to hyperlynx. but I do not success. first I save as my layout in *.hyp file.and opening that's into the hyperlynx, this file be open, but ground plane ( I mean polygons ) do not receive here and all of my ground net to be unconnected, do you know where is my problems??
the best regards
have a good time my friend
mairomaster , 12-19-2016, 01:47 AM
I've done the same before and I don't remember having such problems. Make sure you check the stackup manager (or whatever the name of it is) in Hyperlynx. You will probably need to set the different layers to signal/plane type manually.
robertferanec , 12-19-2016, 10:16 AM
I have had no problems with import. Have you run DRC check on your project in Altium? It looks very unusall, that only GND would be removed.

Also, what you can try is, that if you have some solid layers, try to change them in Altium to be planes. And, as @mairomaster mentioned, double check the stackup manager in Hyperlynx if it was setup correctly.
Arash yahyapour , 12-20-2016, 03:31 AM
Hi Dears Robert and mairomaster
thank you , I a lot of try to solve the problem. but my problem is there , yet. all of GND net and DGND net will be unconnected after import. and my polygon will be remove. my polygon is solid.
I change that to hatched, but my problem was repeated.I send my setting stack layer in Altium and hyperlynx. could you help me please. maybe my software has problem to installation.
mairomaster , 12-20-2016, 07:29 AM
To clarify, do you have the same problem with both ground planes and polygons on signal layers?

In the hyperlynx stack editor, when you scroll the slider to the right, you can assign nets to the plane layers if I remember correctly. Do you have those properly assigned? I am not sure what could be wrong with the polygons. If they pour properly in Altium and have the proper net assignment (as they seem to), they should be transferring normally.
Arash yahyapour , 12-20-2016, 11:07 AM
yes My friend, I have this problem in both of them and all of my polygons, just for polygons. and I have to plane for DGND and i assignment in Altium. also, I assignment all of my polygons to GND and DNAN in altium , I think, I didn't have mistake for define setting in stake layers in altium
I open a demo file for hyperlynx and I compare that, it is the same (gnd and vcc polygons is not connected) but I can see the hatched of plane. however, I can not see the hatched in my file.
the best regards
Arash yahyapour , 12-20-2016, 11:14 AM
Dear robert and dear mairomaster : Wishing You a Merry Christmas and a Happy New Year 2017
robertferanec , 12-21-2016, 10:18 AM
- Is it only GND and DGND or also other polygons? Do you have same problem with polygons connected to different nets e.g. power polygons?
- What version of Altium do you use (maybe there is something wrong with the latest Altium(?))
Arash yahyapour , 12-21-2016, 10:57 AM
I have just two kind of polygons "DGND" and "GND" I get that my hyperlynx has problem with only polygons. the net of that's is not important, I tested it's. could you send a picture of the correctly defined in your hyperlynx please, I want know how it show if it has been connected all component to GND polygon? my Altium is 10.39 copyright 2011
thank you
robertferanec , 12-21-2016, 11:07 AM
You can download for example our iMX6 Module project and try it: http://www.imx6rex.com/ Let me know if you have same problem.
Arash yahyapour , 12-22-2016, 08:13 AM
Okey my friends, I found my problem, I success to do polygons connections, thank you for your recommendations.
robertferanec , 12-22-2016, 12:50 PM
Please, do you know what exactly was the problem? Your solution can help also other people.
Arash yahyapour , 12-23-2016, 09:01 AM
of course, that problem was for bad installation. I install the software again, my problem was solved
robertferanec , 12-23-2016, 10:14 AM
Thank you @Arash yahyapour for letting us know.
Arash yahyapour , 12-26-2016, 05:25 AM
Hi my friend, I do not get it: some layout of DDR2 PCB are include the series resistors and external pull up to 1.8V, but a DDR2 chip, for example Micron has three internal pull up resistors,that you can select to 50 ohm , 75 ohm , 150 ohm , my question: why we need the series resistors and external pull up, while we have the pull up resistors in inside the memory chips?. could you please elaborate on it more?
the best regards
robertferanec , 12-28-2016, 03:24 PM
Very hard question The proper way to understand this is to run some simulations and see what the differences are. The results will be different between layouts, boards, stackups, connections, topology .... More options you provide, more options you can have to tweak your design to get maximum performance.

Generally you may find recommendation to use series termination resistors, however in many designs there is simply no space or it would be too difficult to do layout. So if memories are soldered down to the CPU board, in many designs you will not find series termination resistors.

The termination resistors on ADDR/CTRL/CMD are used in fly-by topology to keep the signal quality as good as possible (e.g. minimize reflections from the end of track). T-branch topology may not need external termination.

The best approach is to follow design guides and reference designs.
Arash yahyapour , 12-29-2016, 12:58 AM
Yes, you are right, I did simulate and I found that is no need the series resistors in my layout. and I found dependence of matching or mismatching impedance (ZO) to 1- setting of stackup layer 2- topology of connections.
matching of connection will be better if I remove series resistors from my layout. so I re-change my layout for fifth time, dear Robert, in new layout I using swapping pin and I found that it is better and you are right, and I doing that , but I don't know what happen to me when I do to design flowchart of program. I just know it is possible. thank you My friend have a nice holiday.
Rogelio , 01-06-2017, 09:31 AM
Hi Robert,

Your Schematic & PCB Design Course mentioned the T branch topology and the fly by for the DDR3, I have some details as I have to route 2 DDR3 on board.

The PCB is 6 layers and one of my concerns is the propagation time for point to point lines as for my worst case I got 55ps difference between DQS and a data line, DQ routed on external and worst case on internal layers. (I used Saturn calc for propagation time on track & via)

+Is this time difference too much or the DDR3 can handle this difference? MT41K512M16HA-107 :A

For the length match for Address & control lines:
I first did it to the first DDR3.
then to the second DDR3 removing the stub to get the real distance from the Up to the second DDR3.
Then I’ll be removing the stubs from both DDR3 and length matching from the Up to the terminators.

+ I would like to have your comments about my procedure to length match the segments.
Still I need to verify the worst case for daisy chain signals (add,clk,etc), my guess is that will be very close to the 55ps also as I used internal layers form DDR3-A to DDR3-B.
I used Saturn to make the calculations.
The tech note said to daisy chain the DDR's.
I also know which are the best practices, but engineering bought an evaluation board which was routed in 6 layers.
I want to take everything in count to make it work in 6 layers.
I have the stack to have 50 ohms in each layer also 100 for diff pairs.


Arash yahyapour , 01-06-2017, 10:15 AM
Hi dear, could I answer you?
Rogelio, 01-06-2017, 10:22 AM
by the way what do you use to simulate the signal behavior?
Arash yahyapour , 01-06-2017, 11:17 AM
so, what is your frequency of CLK? if it is high or if it is comparable with 55ps ,so it will be important to do less than 50. the evaluation boards are for training. they are not industrial boards and you can't used in industrial, so those are not criterion for your final layout. if your frequency of communication between driver and DDRx is high:
- Z0 from driver and also DDRx is very important : - your trace length should be as short as possible.
- select of suitable stack up layer is very important thickness between layers and number of GND plane, "Er" for dielectrics and ...
if your wiring will be mismatch, you will be have reflection in output of data line or Address. and overshoot and undershoot will be high, noise of line will be high and your DDRx don't work or It work but thay DealTime will be less.
I sow your layout. if you use only two DDR , you can place in both of board face to face, and use swapping pin in your DDRx it is better.
I use hyperlynx for simulation.
Rogelio , 01-06-2017, 12:08 PM
I agree, I need to show to the board all the facts, the impedance will be controlled for each layer i dont have trouble with that.
the system uses 32 data bits will work to place it on the bottom?
How many layers do you recommend? and how do you arrange them?
to do something good I think I will need 10

• Timing – cycle time
– 1.07ns @ CL = 13 (DDR3L-1866)
robertferanec , 01-06-2017, 02:07 PM
Is this time difference too much or the DDR3 can handle this difference? MT41K512M16HA-107 :A
@Rogelio Basically, I do not use propagation delay to do length matching for couple of reasons. Some time ago I answered similar question here: http://www.fedevel.com/designhelp/fo...dr3-lpddr-ddr3

I would like to have your comments about my procedure to length match the segments.
- This video may help you: Altium – How to use xSignals ( in Fly-By, T-Branch + Other useful things )
- Also, have a look at our OpenRex design (download the Altium files). Check how we did the layout there. It may be very similar to what you are doing, just OpenRex uses 4 memories: http://www.imx6rex.com/open-rex/

by the way what do you use to simulate the signal behavior?
If needed, I would recommend Hyperlinx - they have a nice wizard for memory simulation.

I also know which are the best practices, but engineering bought an evaluation board which was routed in 6 layers.
I think, the most critical part will be fanout of the BGA and how many power planes you will need. If you have enough space and if the BGA pins are ordered for an easy fanout, it may be possible to use 6 layers, however normally it is not the case

Maybe this can help: 3 STEPS How to determine / calculate number of PCB layers
Arash yahyapour , 01-08-2017, 05:10 AM
Hi dear Robert. my DDR2 controller can not support ODT pin in DDR2 memories, in the controler's datasheet writen: "On-die Termination" and connect to ground. but, I am goin to connect to VDD=1.8V directly for enable ODT. and useing it's
Is there any problem? could you help me please?
robertferanec , 01-09-2017, 09:32 AM
If you are not sure, provide both options: pull up + pull down resistor and test the board. You can then decide ....
Arash yahyapour , 01-09-2017, 10:02 AM
Ok, But I don't want use those resistors because the compaction of my board will be high, if it be possible, I do not use from they.
ODT pin is a pin that , for enable or disable ( On or Off) and internal resistor's selector is a two bit in address bus (i read in micron datasheet A2 & A6).
For enable of ODT pin I want use a IO pin from controller. A common pin or normal IO pin. what do you think??????
Rogelio , 01-09-2017, 10:09 AM
Good morning Robert,
I was able to separate Address from control I routed both on internals, but seems I'll need to do the same but using 2 different internal layers to pass over the Address for the Data and data control lines,
I'm going to need 3 or 4 layers for HS signals, will be enough to use a 10 layer PCB? or shoud I go to 12?

Top sig
PWR mixed
HS ( full plane under HS sig) with coupling caps to GND near vias
Bott sig

this does not look too good for the layer near PWR but I might manage to have an unbroken section under it.

for 12

PWR 3.3
PWR mixed
Bott sig

Do you have a better stack order?
Its complicated to go out of the uP in the same layer with the whole bunch for address or Data.
Thanks for your help
robertferanec , 01-09-2017, 12:21 PM
@Arash yahyapour It's really up to you Be sure, you can control the IO pin before you activate the memory, be sure it has correct initial (after reset) level. Also, you only need two resistors to support the pull up / down option.
Arash yahyapour, 01-11-2017, 03:40 AM
thank you, like for you
robertferanec , 01-09-2017, 12:27 PM
@Rogelio some time ago I wrote a post which you can find on Altium blog. Have a look it can help you: How to Route DDR3 Memory and CPU fan-out

Also have a look at our reference designs, how we routed the individual groups. You can download Altium files of our open source projects from: http://www.imx6rex.com/

PS: What are the tracks routed on the last picture? Are this ADDR/CMD/CTL or they include also DATA tracks?
Rogelio , 01-09-2017, 12:57 PM
I grouped ADD0 to 15 and CLK, and on the other layer BA, RAS, CKE CS,CAS, WE, ODT, RESET. Should I move the CLK with the control signals, I haven't grouped the data signals yet, I'm trying to figure it out how to.
I just downloaded the example, I'll check it, thanks.
robertferanec , 01-11-2017, 10:34 AM
@Rogelio you can group and route ADDR & CMD separately, that is fine. CLK is a group itself. Have a look for example on iMX6 Design guide (google for "iMX6 Design guide"). That may help you with groups and routing: http://cache.nxp.com/assets/document...6DQ6SDLHDG.pdf
Arash yahyapour , 01-13-2017, 09:07 AM
Hi dear Robert
in simulation I have AC overshoot and undershoot in driver pins (SAM9g45) (between 160mv to 300mv) and I was try to resolve their by change in value of series resistor. but I can not success. Of course, signals have been received in memory pins don't have any AC over/undershoot .is it normal? if No, how can I resolve their?
do you see how different between reading signal and writing signal, If I adjust the resistors for writing,...so reading signal will be fail.and if I adjust the resistors for reading,...so writing signal will be fail. it is funny. could you help me please. Thank you.
robertferanec , 01-16-2017, 01:21 PM
Signal depends on many factors, not just series termination resistors e.g. external termination, internal termination of memories and memory controller, routing topology, placement, layout, ..... Very often you will get different results for Read and Write. If you need to simulate memory interface, try Hyperlynx memory wizard, that may help you (it also tells you if your layout pass or fail).
Arash yahyapour , 02-02-2017, 08:28 AM
Hi dear Robert I think my layout about DDR2 with 133MHz finished. I simulated it's with Hyperlynx single signal one by one. the signals of DQX and DQS and Address and commands were good. I checked with eye diagram and they were nice signals. after that I did "Run DDRx Batch simulation" and set all of parameters carefully. after run, the result simulation been fail, status was fail. I searched the problem and find that, problem is in initializing of driver " SAM9G45_TFBGA324". the massage of error is :
"** Error **: Missing driver model; unable to simulate;
** Info **: Initialization of drivers failed!"
I did assign model of driver. it is " IBIS Signal: sam9g45_tfbga324.ibs "
could you help me please . what is my problem.
the best regards.
mairomaster , 02-03-2017, 01:58 AM
Do you have IBIS models for your DDR as well? It is a bit difficult to troubleshoot such problems from a distance.
Arash yahyapour, 02-03-2017, 02:12 AM
Yes, I have . it means , it is default file in software and during to assign model, I found it and define, but my problem is in side of driver,and the software didn't has IBIS model for driver in it's library. I searched in Atmel site and downloaded it's.
robertferanec , 02-04-2017, 10:18 AM
The best would be maybe if you talk to your Hyperlynx support. I do not own the software, I only can use it occasionally when some of my clients have it. Also as @mairomaster explained, it's not so simple and it takes some time to simulate designs - that is the reason why we do not do it for every board - we only simulate when we have to break too many rules.
Arash yahyapour , 02-22-2017, 09:42 AM
Hi dear Robert my design is finished. I want to make it. we have a large variety of board. so I can not select their.1- which one is suitable for my design?? I sow your stack up parameters. 2- for example: VT47-106 VT47-1080 VT47 what different between their??
3- you written in your table about "impedance" . for example: target impedance= 90 calculated impedance= 90.060
- how to find your target impedance??
- how to calculate that ​impedance??
please kindly to answer me
the best regards
robertferanec , 02-22-2017, 05:01 PM
@Arash, you need to talk to your PCB manufacturer. This should help you: http://www.fedevel.com/welldoneblog/...n-pcb-stackup/

- Target impedance should be specified in your design guide. If you have no design guide, one of the nice generic documents is "COM Express Design Guide". Just google for it (starts from page 182): https://www.picmg.org/wp-content/upl...2013-12-06.pdf

- Impedance calculation: you should leave this on your PCB manufacturer. If you still would like to calculate the approximate track geometry, you can for example use the free Saturn PCB Toolkit: https://www.saturnpcb.com/pcb_toolkit.htm
ankit.ahlawat , 05-11-2020, 06:37 AM
Hi Robert Sir,
My controller support DDR3L having four bytes data bus. Controller's Datasheet says that these four bytes are swappable and swappable bits in same byte lane.
My design having 2 memory chips so could i make byte swap combination like below ->
BANK0 -> Data Group Lower Byte of First Memory.
BANK1 -> Data Group Lower Byte of Second Memory.
BANK2 -> Data Group Upper Byte of First Memory.
BANK3 -> Data Group Upper Byte of Second Memory.

For more clear see attached schematics picture ->
robertferanec , 05-15-2020, 02:28 AM
Yes, I have done that couple of times.

PS: some datasheet may say, that lowest bit should be always first, I see you kept them that way. Also, be careful about DQS and DM signals, but I see you have them correctly placed.
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