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venkateshn@slntech.com , 09-01-2015, 11:05 PM

Hi,
can anybody suggest me DDR2 length matching details between groups like Data,Address,Control and relationship with Clock and i gone through the freescale document there they have suggested notes which is attached in the post and kindly verify the DDR2 Placement and length matching details
Note: i am using MPC8308(PowerQuicc II pro) Freescale processor

Regards,
Venkatesh

robertferanec , 09-02-2015, 01:32 AM

@venkateshn@slntech.com I guess, the problem is, that you would like to use ECC, that means three chips on the ADD/CMD/CTL bus and that makes the design more complicated. Is that correct? Did you try to find any DDR2 ECC reference designs with three chips?

I had a look at Freescale MPC8308 RDB Design Files. It looks like, they do not use ECC and they do not use termination resistors. In your design, you added the third memory chip + termination resistors. Did you do it by yourself or you found a design where did you copy it from?

robertferanec , 09-02-2015, 02:34 AM

I really would try to find a DDR2 reference design with three memory chips and see how the other people do it. If I found nothing, I would consider two options:
1) I would probably rotate the ECC memory chip by 180 Deg. I would also consider to place all the termination resistors in the place where the ADD/CMD/CTL splits (use minimum stubs). I would try to make all the three branches same length (from split to each memory chip). And, I would simulate it to see if the signals are ok.
2) Do not use ECC

About the length matching requirements. There are sometimes differences between different manufacturers. Please where did you get the "ROUTE BY GROUP METHOD" picture from?

BTW: you may want to add decoupling capacitors also close to the termination resistors - usually between VTT and 1V8 or GND

I found these two documents (there are more). You may want to have a look:
AN2910: Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces or Download here
AN408: DDR2 Memory Interface Termination, Drive Strength, Loading, and Design Layout Guidelines or Download here

venkateshn@slntech.com , 09-02-2015, 02:50 AM

Thanks Robert for your replay,

I found ROUTE BY GROUP METHOD information from frrescale application note AN4054 for IMAX processor,


Regards,
Venkatesh N

robertferanec , 09-02-2015, 03:12 AM

AN4054 seems to me like a good document. I would probably follow it.

venkateshn@slntech.com , 09-02-2015, 04:07 AM

My board routing is completed now i suppose to go for Length matching of DDR2 interface so kindly suggest me how to simulate delays between different groups like address,data and clock.

Note:what you will suggest to DDR2 placement.


Regards,
Venkatesh N

robertferanec , 09-02-2015, 04:31 AM

Did you route it as shown on the picture MPC8308 DDR2 SDRAM PLACEMENT.JPG?

I do not normally simulate, but if I have to, I use Hyperlynx - they have a nice DDRx Wizard which helps you with memory simulation. However, only few of our customers own the licence as the software is expensive. I am not sure what other people are using, but if you would like to simulate just the reflection / crosstalk on the address tracks, you may be able to do it even in Altium. I do not use Altium simulator, so I can not help you with that, but I think it's not difficult, some time ago I tried that.

venkateshn@slntech.com , 09-02-2015, 04:43 AM

Yes placement is as per the image .JPG attached.kindly suggest me how to do length matching in this case i.e between groups.


Regards,
Venkatesh N

venkateshn@slntech.com , 09-02-2015, 05:03 AM

Hi Robert,
I gone through the MPC8308 RDB PCB file and i noticed following length matching details,

length details between different signals,

1. Address - 3392 mils ( it includes total Etch i.e from Controller to two Devices)
2. Data -2004mils (it includes controller to one device)
3. RAS -3339mils( it includes total Etch i.e from Controller to two Devices)
4. CAS -3329.55mils( it includes total Etch i.e from Controller to two Devices)
5. WE -3366mils( it includes total Etch i.e from Controller to two Devices)
6. ODT -3508mils( it includes total Etch i.e from Controller to two Devices)
7. CKE -3416mils( it includes total Etch i.e from Controller to two Devices)
8. CS -3382mils( it includes total Etch i.e from Controller to two Devices)
9. CK1 -2987,32mils(it includes total Etch i.e from Controller to two Devices)
10. CK2 -2987.33mils( it includes total Etch i.e from Controller to two Devices)

With the above data I can summarize that,

1. From Address to data there is a 1300mils difference.
2. All control signals are length matched within 100 mils length difference.
3. From Clock to address around 400 mils difference.
4. From clock to data 1000 mils difference.

Regards,
Venkatesh N

robertferanec , 09-02-2015, 05:19 AM

For length matching I would probably follow the ROUTE BY GROUP METHOD picture.

However, I would really consider to change the placement and re-route it. For example, I believe, in the current placement, the ECC data lines are probably longer than CLK (I mean, the length of ECC data lines between CPU and ECC memory seems to me longer than the length of CLK signals between CPU and ECC memory pins) - which may not be the best way to do it and you may need to add a lot of extra length to the ADD/CMD/CTL lines to meet the length matching requirements. I would handle ECC lines as data group.

In your current placement, it may be quite difficult to follow the length matching rules which you attached in the ROUTE BY GROUP METHOD picture. Also, placement of the VTT resistors may not be optimal - they add stubs and asymmetry to the ADD/CMD/CTL tracks. Try to simulate it, and I guess, you may see, that the placement of termination resistors will make difference in signal quality.

venkateshn@slntech.com , 09-02-2015, 05:29 AM

Then how you will propose placement in this case and can you please let me know how to route VTT.


Regards,
Venkatesh N

venkateshn@slntech.com , 09-02-2015, 06:21 AM

If i rotate ECC chip by 180 deg it will overlap on processor, find the attached placement file for your reference.


Regards,
Venkatesh N

venkateshn@slntech.com , 09-02-2015, 06:42 AM

you mean that to place ECC chip in between two other devices.


Regards,
Venkatesh N

venkateshn@slntech.com , 09-02-2015, 06:46 AM

ECC chip is placed on bottom side

robertferanec , 09-02-2015, 06:48 AM

I don't know exactly what could be the best placement - you will need to play with it and think about how the layers will be used. The goal is to have same length between the VIA (where ADD/CMD/CTL signals splits) and each memory chip + have option to place termination resistors very close to the VIA. We will try to draw an image to explained it better.

robertferanec , 09-02-2015, 06:54 AM

How many signal and power/gnd layers do you have? Where exactly data / add / cmd / clk signals are placed on the CPU?

venkateshn@slntech.com , 09-02-2015, 07:01 AM

Thank you very much Robert for your great time and kind support,
OK i will do length matching as per the byte group method and i will send you the final PCB file for your kind review and feedback.



Regards,
Venkatesh N

robertferanec , 09-02-2015, 07:05 AM

@venkateshn@slntech.com please, I try to help, but I do not review designs. Thank you very much for understanding.

robertferanec , 09-02-2015, 08:16 AM

Maybe we would try to do it this way - see the attached picture. However, I am not saying that this is the way you should do it nor that it is the best way to do it. It is just an initial idea.

venkateshn@slntech.com , 09-10-2015, 10:39 PM

Hi Robert,
I am using following 8 layer stackup, in this my doubt is i am using only one GND can you check is this ok r not,

Regards,
Venkatesh N

robertferanec , 09-11-2015, 12:16 AM

Hi @venkateshn@slntech.com it really depends on your circuit and design. You will need to be aware of your DDR2 track routing, reference planes, possible crosstalk between L3/L4 and currents flowing through the GND plane.

I normally don't use 8 layer PCB, because I always prefer to have at least one solid neighbour GND plane per high speed signal layer.

venkateshn@slntech.com , 09-11-2015, 01:12 AM

Thanks Robert for your kind suggestion,
now i have changed the above stackup as per below, kindly check is this ok.

Regards,
Venkatesh N

robertferanec , 09-11-2015, 01:34 AM

@venkateshn@slntech.com I am not really sure what would you like to hear I can not say if its good or bad - if I was doing it, I would use 10 layer stackup ... for example, from my experience one PWR plane is not enough.