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iMX6 Rex Development Baseboard Layer Stack
Kostas_P , 03-04-2016, 01:16 PM
Hi Robert,
I would like to ask you regarding to the iMX6 Rex Development Baseboard layer stack.
You route your PCIe signals(RX, TX, clock) on the layer 3 where on layer 2 is GND and on layer 4 split power polygons.
Is it acceptable to have 1 solid layer on the top of the signal layer and the other layer(bottom of signal layer) to be a split power polygons with regards to current returns?
I am designing a riser card where the key of the PCIe connector should be placed 180 degrees from its normal position due to mechanical restrictions. To achieve this the CPU support lane reversal which i wont need to cross the PCIe data signals. However, the PCIe clock, smclk, smdata, pcie_wake and pcie_rst will need to travel from the left side of the finger connector to the right of the PCIe connector. To do that, i will need to use a minimum layer count of 6 layers.
My plan is to use the following layer stack:
L1- SIGNAL
L2-GND
L3-SIGNAL (PCIe clock, smclk, smdata, pcie_wake and pcie_rst)
L4-POWER(12v)
L5-GND
L6-SIGNAL
Would it be OK having a 12V power reference plane below the signal layer 3? i am cautious about the PCIe clock signal.
Thank you very much!
I would like to ask you regarding to the iMX6 Rex Development Baseboard layer stack.
You route your PCIe signals(RX, TX, clock) on the layer 3 where on layer 2 is GND and on layer 4 split power polygons.
Is it acceptable to have 1 solid layer on the top of the signal layer and the other layer(bottom of signal layer) to be a split power polygons with regards to current returns?
I am designing a riser card where the key of the PCIe connector should be placed 180 degrees from its normal position due to mechanical restrictions. To achieve this the CPU support lane reversal which i wont need to cross the PCIe data signals. However, the PCIe clock, smclk, smdata, pcie_wake and pcie_rst will need to travel from the left side of the finger connector to the right of the PCIe connector. To do that, i will need to use a minimum layer count of 6 layers.
My plan is to use the following layer stack:
L1- SIGNAL
L2-GND
L3-SIGNAL (PCIe clock, smclk, smdata, pcie_wake and pcie_rst)
L4-POWER(12v)
L5-GND
L6-SIGNAL
Would it be OK having a 12V power reference plane below the signal layer 3? i am cautious about the PCIe clock signal.
Thank you very much!
robertferanec , 03-05-2016, 11:49 PM
Tricky question.
- If possible, we try to keep both planes (above and below the tracks) solid and big.
- If not possible, we still try to keep the GND plane solid and big, but we try to draw power planes above related tracks & components.
- If not possible, we can not do much
... still we try to have at least one big GND plane
When we design stackup, we normally place the solid GND plane closer to the signal layer than the layer with split Power planes - so the solid GND plane has much higher effect on the tracks than the layer with split power planes.
I am not sure how the 12V plane is connected, but it may not be the ideal reference plane.
- If possible, we try to keep both planes (above and below the tracks) solid and big.
- If not possible, we still try to keep the GND plane solid and big, but we try to draw power planes above related tracks & components.
- If not possible, we can not do much
... still we try to have at least one big GND planeWhen we design stackup, we normally place the solid GND plane closer to the signal layer than the layer with split Power planes - so the solid GND plane has much higher effect on the tracks than the layer with split power planes.
I am not sure how the 12V plane is connected, but it may not be the ideal reference plane.
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