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Arunprakaash6 , 05-05-2023, 12:10 PM

Hello Engineers,

I am doing PCB layout with 2x DDR4 with Fly-By topology and 2x DDR4 with Clamshell topology.

Flyby Topology:
I have placed Both DDR in top side in series and I have routed the Address signal from FPGA to DDR1 (Length matching done). DDR1 to DDR2 (Length matching done). DDR2 to Termination (Do I want to length match this also?)

Clamshell Topology:
I have placed one DDR on top side and another DDR on Bottom side directly each other. I have routed address signals from FPGA to Both DDR's by T-branch (Length match done). Routing from that T-branch via to Termination resistor is also done (Do I want to length match this also?)

robertferanec , 05-11-2023, 03:58 AM

keep them short and I do not length match them.

PS: if you are not sure, you can always have a look at JEDEC memory modules reference designs, they are free to download.

Paul van Avesaath , 05-25-2023, 03:33 AM

i also do not length match them