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iammituraj , 08-12-2022, 02:57 AM

I have a source synchronous output interface (SDR) in a chip where output data has a large a max. skew of 15 ns from the output clock which is of 20 ns time period, as I can see from its data sheet...The data and clock have go to an FPGA which expects edge aligned data and clock within some allowable skew window +/-5 ns.

How's clock and data traces routed in a typical board in this case? Does the designer adjust trace lengths to make skew = 0? Or both traces are routed exactly similar and the skew will still be 13 ns at FPGA, and FPGA has to take care of this phase shift compensation inside it's logic? 13 ns skew being more than 180 degree phase shift, is hardship in the FPGA design side though.

What would be the best approach / conventional approach here to solve this problem?

qdrives , 08-12-2022, 02:45 PM

Do you have a datasheet or part number?

robertferanec , 08-16-2022, 05:12 AM

You can do length matching. If you are not sure about tolerance, use +/- 10mil (that is often used standard). Don't forget to route all the signals the same way (so they travel on the same layers to eliminate the length in via). Also, keep in mind, signals are travelling different speed on the top / bottom vs inside of PCB, but that may not be critical in this case.