Decoupling capacitors placement
Bermell , 06-25-2022, 05:16 AM
Hello Robert,
Firstly, thanks a lot for your excellent work all these years.
My question is about a strange placement of decoupling capacitors that i have seen in the following video:
Firstly, thanks a lot for your excellent work all these years.
My question is about a strange placement of decoupling capacitors that i have seen in the following video:
Steve.Picotest , 06-25-2022, 06:27 AM
See my EDICON paper on partial inductance this minimizes the mount portion if the inductance, making the capacitor much more effective at high frequencies (DDR, FPGA, etc)
qdrives , 06-25-2022, 09:38 AM
As long as the via's are either:
- Filled and capped
- Solid copper fill
- Filled and capped
- Solid copper fill
Bermell , 06-25-2022, 01:01 PM
Thank you very much for your answers
robertferanec , 06-27-2022, 07:51 AM
@Bermell it is possible to do via in pad ( as @qdrives mentioned ). It has some advantages, as @Steve.Picotest already mentioned, it is better way to connect decoupling capacitors and also sometimes it's done this way if there is no extra space for additional pads. However, it is more expensive, that is why it's not on many boards.
Bermell , 06-27-2022, 12:27 PM
Thank you very much Robert
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