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Impedance of single ended signals
Firasgany7 , 12-29-2020, 07:48 AM
Hello,
Looking at an existing design at the company I work on, I noticed that in the design of TPS54620 DC2DC, the +3V3S_PH signal was defined as
a single ended output with 50 Ohm impedance.
what is the difference between single ended and regular analog output?
why is 50 Ohm is the selected value?
Looking at an existing design at the company I work on, I noticed that in the design of TPS54620 DC2DC, the +3V3S_PH signal was defined as
a single ended output with 50 Ohm impedance.
what is the difference between single ended and regular analog output?
why is 50 Ohm is the selected value?
Steve.Picotest , 12-29-2020, 08:29 AM
This is not a 50Ohm trace, so I don't k ow why it was identifies as such. Single ended output and analog output are the same thing at higher frequency. In the case of this phase node, the front edge ringing is due to the loop inductance of the input cap and pond wires through top and bottom switches back to input cap. This inductance rings with the capacitance of the PH node. This node includes COSS of the. Bottom. FET, the plane, the capacitance of the output inductor and shotkey protection diode if it exists. So minimize capacitance relative to Coss (which isn't usually specified) and all should be well.
Comments:
Firasgany7, 12-31-2020, 06:43 AM
Thanks Steve)
Steve.Picotest , 12-31-2020, 07:05 AM
Glad I could help 
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