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shanesyw , 07-03-2020, 10:57 AM

Hi all,

I just purchased and started the course for Advanced PCB Layout. The course seems to cover the trace layout from processor to the Ethernet PHY. However, since this course only cover the iMX Rex module, the connection through magnetics probably won’t be covered.

The OpenRex or the carrier board for the iMX Rex would have the connection from PHY through the magnetics to the RJ45 jack. I understand the magnetics seems to be included in the RJ45 jack, but would still like to learn how to do the (differential) tracing from PHY to the RJ45 (MagJack). I think there might be some ground plane considerations too, so that’s why I would really like to see how Robert would layout the trace (for the full pipeline) in the video. Where in course material can I find this particular coverage?

I think the aspect of routing/stacking/ground plane design would an excellent area to be covered in the course, considered in the IoT world ethernet connection would be essential for all the boards (well, unless you're talking about wireless...).

I'm trying to implement RMII from STM32F7 through PHY to RJ45 (without integrated magnetics). If the course doesn't cover this, I would like to ask if people can graciously give me some pointers on this.

1) Between the MAC and the PHY, what are the length matching requirements for TXD0, TXD1, RXD0, RXD1, CRSDV, MDC, MDIO, REFCLK?
- Should TXD0, TXD1, RXD0, RXD1, REFCLK be the same length?
- Should MDC and MDIO be the same length, and should their length match the REFCLK?
2) I know there should not be any ground plane below the external magnetics, Is there any other area that I should not have ground plane under at all as well?
3) Between the external magnetics to the RJ45, there are two pairs of TX and RX differential signal Should these two differential pairs be of the same length as well?

A few references I have found so far:

https://resources.altium.com/p/ether...-45-connectors
https://resources.pcb.cadence.com/bl...ting-practices
https://resources.pcb.cadence.com/bl...s-for-ethernet

Thanks in advance for your help.

Shane

robertferanec , 07-04-2020, 01:10 AM

Hi @shanesyw. The course covers also Base baseboard.

There is nothing special about Ethernet signals - these are routed as differential pairs and these are explained in the Advanced PCB Layout course. So, when you follow differential pair routing recommendations, you will be fine when routing Ethernet.

1) It depends on RGMII version (old required to add delay into PCB, it is not normally required now). So, usually all TX similar length, TX_CLK longest. Same for RX. The MDC & MDIO are just like I2C (independent from TX and RX), these signals are used to read and set registers of the PHY chip.

2) I have seen all the kind of boards. I believe, the main problem is ESD - you do not want any ESD pulses jumping from the connected cable to anything on your board. I believe, that is reason for nothing around connector + connection to magnetic. But specific implementation may depend on how ESD is solved on your board or how the whole system looks.

3) I do them same length