Advance Layout Course (Lesson 2) Memory Signals
tariq1996 , 05-15-2020, 08:14 AM
Hello everyone,
In the Advance layout course (Lesson 2), I would like to ask that:
Why did mr.Robert make some memory signal in the cpu a through-hole via and some of them a uVia ? why? is it better if we did a uVia for all the signals?
Example:
DRAM_D[0..7] are uVia.
DRAM_D[17..23] are through-hole Via.
In the Advance layout course (Lesson 2), I would like to ask that:
Why did mr.Robert make some memory signal in the cpu a through-hole via and some of them a uVia ? why? is it better if we did a uVia for all the signals?
Example:
DRAM_D[0..7] are uVia.
DRAM_D[17..23] are through-hole Via.
robertferanec , 05-16-2020, 12:59 AM
It is explained later in the course. This may also help with explanation: https://resources.altium.com/p/how-t...nd-cpu-fan-out
tariq1996 , 05-17-2020, 01:10 AM
Thank you Mr.Robert.
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