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Routing differential pairs (LVDS signals) and impedance matching

Rongard , 03-05-2020, 05:21 AM

I'm working on a custom carrier board for the FPGA (PicoZed). On this board I have to route LVDS signals. There are four differential pair groups (buses) which I have to length match. Also I have to length match within each pair. Maximum operating frequency for the signals is going to be 250MHz. I have a couple of questions regarding all this.

My questions are following:

1. What is acceptable tolerance for length matching or how to deduce this? Currently I just picked 5mil for both (within and across pairs) which I think should be enough, but maybe it's too tight of a tolerance and just unnecessarely complicates things?

2. As the frequency is 250MHz (wavelength is little more than a meters), the transmission line should be regarded as short, so I think impedance matching should not be so strict of a requirement? I'm still trying to keep the diff pairs impedance 100ohms (both ends are terminated with this), but I mean, if I have to choose between length matching and impedance matching I think I should firstly worry about length matching and them impedance matching? Is my understanding correct? I've attached a picture that show some extreme examples of my diff pairs routing, are these okay or should I worry about signal integrity?

3. When doing impedance matching, I need to properly define layer stack-up and then define constraints (width, spacing) for my traces. I've used Saturn tool for that, but the problem is that I have to calculate impedance for the diff pairs on internal layers which have asymmetric dielectric heights. Inserting different heights is allowed, but how to account for the changing dielectric constant. Manufacturing house will manufacture the board using cores and prepregs alternately which have different dielectric constant values. For example PCBWay stack-up examples -https://www.pcbway.com/blog/Engineer...___pcbway.html

robertferanec , 03-09-2020, 12:30 AM
1) I use:
- withing 5 mils within pair (between negative / positive) is standard.
- between pairs - I almost always use 10mils for almost everything what need to be length matched. It may be too strict, but I do not have to spend time searching for specific rules, I am sure it will be ok and it is not much more work as if you would be doing length matching let's say within 100mils. Especially, if there will be a cable connected or other board connected to that interface, I try to keep the signals almost the same to be sure, that it will work even if cable or the other board are not length matched properly.

2) should be both (but for slower interfaces, below 2.5GHz I was more concerned about length matching and it always worked oki - but i always really try to follow both). However impedance matching is also critical, I woudl recommed to watch this my video, it can help to understand it better: https://www.youtube.com/watch?v=ZyoqhJB_E9Q

3) You can use Saturn for approximate calculation, but you always have to speak to a PCB manufacturer to get exact stackup and track geometry for specific impedance. This video may help to understand it better why: https://www.youtube.com/watch?v=f6_svRNJYls
Rongard , 03-12-2020, 01:49 AM
Hi Robert!

Thank you for your help and sorry for the late response, I was on a holiday trip and tried to keep myself away from computer

The videos that you sent was really helpful and educating, thank you! I will be trying to follow your guidelines on length matching.

The PCB manufacturer (PCBWay) unfortunately did not give me very specific rules to follow regarding the stack-up. I asked them about impedance control and which stack-up to use and they basically said that I will have to send them the info about the stack-up I want and they will make adjustments to this and board design to meet the impedance control requirements. I don't know if that's a good or a bad thing

I actually have another concern regarding the timing of the signals in reference to their clock. When routing signals that carry data and also clock signals which are used for clocking in that data, then should I make the clock lines slightly longer than data lines to assure that clock arrives at the BBP later than data? Both devices (AD9361 and Zynq) actually have drivers which should be able to do this themselves (delaying clock), but maybe making the clock lines slightly longer helps in achieving this? Or maybe it will only make the design and timing worse?

Thank you for your great help!
robertferanec , 03-13-2020, 01:00 AM
- I know, that PCBWay has recommended stackups (e.g. this is what I found https://www.pcbway.com/blog/Engineer...___pcbway.html ), but I am not sure if they also have recommended track geometry for different impedance for these stackups (I could not find that information on their website). Normally, for impedance controlled stackup I use for example Exception PCB: https://www.exceptionpcb.com/

- I usually make clock the longest signal in the bus.
Rongard , 03-13-2020, 01:43 AM
I haven't heard about that PCB manufacturer before. I will check those guys out, thank you!

Is there any specific rule how you determine how much longer the clock line should be?
robertferanec , 03-16-2020, 12:21 PM
If there are no specific design rules, it can be longer just a little bit e.g. 1mm
antoniocontursi660 , 03-23-2020, 08:00 AM
Hi Robert,i have a question (maybe you have already answered to it) what is the difference between Signal length an Routed length, that is if i create a rule in order to obtain the routed matched, it's possible that the signals are not matched in lenght?
Rongard, 03-23-2020, 08:23 AM
Interactively Tuning the Lengths of Your Routes on a PCB in Altium Designer | Altium Designer 24 Technical Documentationhttps://www.altium.com/documentation/altium-designer/length-tuning-adThis page looks at the PCB Editor's support for length tuning - being able to match the lengths of routes, by inserting variable amplitude tuning patterns, to ensure that timing-critical signals arrive at their target pins at the same timeSignal length and its relation to routed length is defiend in this article.
antoniocontursi660 , 03-23-2020, 08:08 AM
Sorry but i have another question, how can i change the rules priority? Altium seems not to do it, i have to duplicate the rules and it put it in another position. Some tips?
robertferanec , 03-24-2020, 03:04 AM
Routed vs Signal length
From the document what @Rongard linked:
- Routed Length = sum of the lengths of the placed track segments.
- Estimated Length = current Routed Length + distance from current location to target pad (length of the remaining connection line).
- Signal Length = current Routed Length + Manhattan (X + Y) distance from current location to target pad.

Rules priority

antoniocontursi660 , 03-24-2020, 03:09 AM
Thank you very much Robert
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