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Question on DRAM matching from Lesson 9 of Schematic and PCB Course

Tom Yunghans , 02-24-2020, 05:29 PM
Hi Robert,

I have been working on Lesson 9 of the Schematic and PCB Course. I hooked up the missing signals in the VOIPAC - Easy version of the DDR3 layout in Lesson 8 (see file below)

In lesson 9, I have been trying to length match those DDR signals. I followed your "copy and paste" method on the DDR3 lines to route the two upper DDR memories as you described in the video, and then used the PCB panel to adjust the lengths so the total length from processor to those 2 DDR chips matched pretty closely. However, in the video I do not believe that you discussed how to handle the connections to the lower two DDR devices. It doesn't seem trivial to try and match the total length of each signal to all the other signals, as well as matching the two Layer 8 lengths for each signal (as I see in your spreadsheet below). Do you have some advice on how to accomplish this? Did you not discuss this because it is obvious, and I am just not seeing the obvious solution? I looked through the forum and didn't see any questions/answers on this topic.

Thank you!

Tom Yunghans
Carlsbad, CA
robertferanec , 02-26-2020, 09:07 AM
I am not 100% sure what you mean, but, the last segment is the same between top and bottom memory. So if the top memories are lenght matched, the bottom will be length matched too. Does this answer your question?
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