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Roky , 01-01-2020, 05:22 PM

Hi
I ' m checking the baseboard schematic of Voipac for Schematic and PCB design course.
I found few.. problems in schematics and I would need to ask here about these (in the MMC sheet):
​
Why this configuration for A0, A1,A2 and WP pins? At half of 3.3V(Veprom) ?? neither HI ..neither LO ...it is a metastable state

and even in the other IC FLASH 32Mbit for WPE pin:
​

And ...what about CSPI1_MISO_3v3 signals? should it need a pull up resistor?
There is no pull up resistor in all the schematics for thi signal,
but it is a line shared among several open drain driving pins.

For the two 0R resistors on CSPI1 signals I think they are not used both,
I guess they are for changing/selecting whitch signal (SS0 or SSI) should be drive the CE line.


Same problem for metastabiliy here for I2C_SDA and I2C_SCL lines in USB sheet:



thank you very much for your attention
and ...Happy New Year!

Rocco

robertferanec , 01-02-2020, 06:00 AM

VOIPAC Schematic is used to point out some interesting stuff. In this case, a proper variant should be defined - and fitted / not fitted components should be marked. This means, only one of the components will be fitted in reality, however if this is not reflected in schematic, then schematic may be confusing - and that is the point what we can learn from this schematic.

Happy New Year

Roky , 01-02-2020, 06:33 AM

OK ..I got the point for learning using variants...

and ...what about CSPI1_MISO_3v3 signals? should it need a pull up resistor?

I guess I should add at least one pull up....I did not find any information about this
in the SPI IC datasheets used in these schematics
but I know that, in SPI protocol, the "Master Input Slave Output" line
has a multiple drivers (slave devices) in open drain (or collector)
configuration so it should need a pull up resistor.
Am i wrong?

thank you always for your fast reply

robertferanec , 01-02-2020, 11:47 PM

This is sometimes tricky for several reasons:
- you do not know how this signal is connected on the module (very often, if an external pull up/down is required, it would be handled by module to make it easier for people to design baseboards)
- many CPUs support enabling / disabling internal pull ups/downs. So it can be handled by software
- some SPI chips do not support open drain

So, it depends on design and implementation.

Roky , 01-03-2020, 03:02 AM

I checked the wrong IMX53 datasheet, about an internal pull up resistor
but now I have found this on its app manual:



..as you said

for your last point ..I m sorry but I think that there are no other physical possible solutions
different from the open drain (or collector) for a topology where multiple drivers
need to drive a single line ...due to a contention problem



Anyhow I will simply do what you have suggested in your lessons:
"If you are not sure about a schematic part ....just put there!!"

thank you

robertferanec , 01-03-2020, 03:21 AM

"If you are not sure about a schematic part ....just put there!!"
-

"but I think that there are no other physical possible solutions"
- yes, you are correct. And in some cases it is not possible to connect multiple chips on one SPI.