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Asymmetric stripline impedance

suleymancskn , 12-11-2019, 02:05 AM
Hi, I am interested in DDR3 design. The processor which I use in my project is A64. 6 layer pcb design. I have problems with stack structure.

I have my stack structure: Top layer, GND, Signal Layer2, Signal Layer3, POWER, Bottom.

I want to calculate impedance for the line in signallayer2. Which calculator should I use and How should I specify the H parameter.

robertferanec , 12-11-2019, 05:12 AM
For approximate impedance calculation I use free Saturn PCB toolkit: http://www.saturnpcb.com/pcb_toolkit/ Have a look here: https://youtu.be/O4T9y_aIItA

About H: depends how good the power plane is, but often GND and Power planes are used as reference planes - so that would be the distance e.g. L3 (Signal) to L2 (GND) and L3 (Signal) to L5 (POWER). If you are not sure, take existing stackup and try to re-calculate the numbers, here are some examples of existing stackups: https://welldoneblog.fedevel.com/201...your-projects/

PS: you still may need to double check your calculations with your PCB manufacturer as only PCB manufacturer can give you the correct number
suleymancskn , 12-11-2019, 06:15 AM
Thank you so much R. Feranec. Information was very useful to me.

I have another question. I am using 2 piece DDR3.

Is there a list of rules I can take as an example for setting length? Each resource can have different rules.
Should all lines be shorter than CLKP&CLKN ? From what I see, the address lines can be long. Is there a limit on the length of the address lines?

My design rules have been prepared with the link below.

Can you help with length tuning rules?
robertferanec , 12-13-2019, 01:11 AM
There are differences between chips and it is always recommended to follow recommendations for specific chip (I have seen design guides where CLOCK was the longest signal, but I have seen design guides where clock could be also shorter). If there are no recommendations, the iMX6 design guide is a good point to start with (usually you would like to have the CLOCK the longest).

Some time ago we created this picture - it is just a different way to show their table, maybe it can be helpful:

Paul van Avesaath, 12-18-2019, 01:13 AM
i have seen this image many times now... there are a lot of topics already explaining this..
Lakshmi , 12-14-2019, 12:17 AM
Hey @@suleymancskn, I still suggest you take a look at the reference design on the processor for the Layer stack up once.
I'd suggest you go as:
L1: S1 with ground pour.
L2: Continous GND Plane
L3: Signal with Gnd pour
L4: Power and Signal
L5: Continuous GND Plane
L6: Signal with GND pour.

If you feel you don't have space with this Layer stack up you can go with 8 Layer also. Keep in mind you always need a reference for Signal and Power. And that reference can be either GND OR Power. Most likely better to go with GND. (You'll use Power as a reference when Signal IO level is same as the Power).

About the Impedance calculation:
You can use any of the impedance calculators as @@robertferanec suggested Saturn PCB is open-source OR you could also go with licensed you'll have more flexibility.
But You need to cross-check with Manufacturer also as they are one who knows how it performs as the material is very well known to them.
Also, you can use some of the tools for pre and post Layout simulation like ADS etc..

suleymancskn , 01-22-2020, 12:01 AM
Hi, I completed my first ddr3 design. But i have some questions.The length of the address lines is 58mm. I set the clock line length to 65mm. What do you think should be the clock length?
Paul van Avesaath , 02-05-2020, 03:32 AM
in my experience clock lines should be longer than the addres lines,so i think you are good with this difference.
robertferanec , 02-05-2020, 11:21 AM
Design guide of the CPU will tell you what are the requirements. As @Paul van Avesaath said, clock is usually longer, but there may be big differences between designs. The maximum and the minimum clock difference from address group is usually specified in design guide and that value is important to follow.
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